^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OWL SoC's Pinctrl definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: David Liu <liuwei@actions-semi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __PINCTRL_OWL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __PINCTRL_OWL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OWL_PINCONF_SLEW_SLOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OWL_PINCONF_SLEW_FAST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MUX_PG(group_name, reg, shift, width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .name = #group_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .pads = group_name##_pads, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .npads = ARRAY_SIZE(group_name##_pads), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .funcs = group_name##_funcs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .nfuncs = ARRAY_SIZE(group_name##_funcs), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .mfpctl_reg = MFCTL##reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .mfpctl_shift = shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .mfpctl_width = width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .drv_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .drv_shift = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .drv_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .sr_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .sr_shift = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .sr_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRV_PG(group_name, reg, shift, width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .name = #group_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .pads = group_name##_pads, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .npads = ARRAY_SIZE(group_name##_pads), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .mfpctl_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .mfpctl_shift = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .mfpctl_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .drv_reg = PAD_DRV##reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .drv_shift = shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .drv_width = width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .sr_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .sr_shift = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .sr_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SR_PG(group_name, reg, shift, width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = #group_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .pads = group_name##_pads, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .npads = ARRAY_SIZE(group_name##_pads), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .mfpctl_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .mfpctl_shift = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .mfpctl_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .drv_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .drv_shift = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .drv_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .sr_reg = PAD_SR##reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .sr_shift = shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .sr_width = width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* PAD PULL UP/DOWN CONFIGURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .reg = PAD_PULLCTL##pull_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .shift = pull_sft, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .width = pull_wdt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct owl_pullctl pad_name##_pullctl_conf \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ST_CONF(st_reg, st_sft, st_wdt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .reg = PAD_ST##st_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .shift = st_sft, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .width = st_wdt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct owl_st pad_name##_st_conf \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) = ST_CONF(st_reg, st_sft, st_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PAD_INFO(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .pad = name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .pullctl = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .st = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PAD_INFO_ST(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .pad = name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .pullctl = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .st = &name##_st_conf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PAD_INFO_PULLCTL(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .pad = name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .pullctl = &name##_pullctl_conf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .st = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PAD_INFO_PULLCTL_ST(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .pad = name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .pullctl = &name##_pullctl_conf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .st = &name##_st_conf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OWL_GPIO_PORT_A 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OWL_GPIO_PORT_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OWL_GPIO_PORT_C 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OWL_GPIO_PORT_D 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OWL_GPIO_PORT_E 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OWL_GPIO_PORT_F 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, _intc_ctl,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) _intc_pd, _intc_msk, _intc_type, _share) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [OWL_GPIO_PORT_##port] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .offset = base, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .pins = count, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .outen = _outen, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .inen = _inen, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .dat = _dat, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .intc_ctl = _intc_ctl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .intc_pd = _intc_pd, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .intc_msk = _intc_msk, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .intc_type = _intc_type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .shared_ctl_offset = _share, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum owl_pinconf_drv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) OWL_PINCONF_DRV_2MA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) OWL_PINCONF_DRV_4MA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) OWL_PINCONF_DRV_8MA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) OWL_PINCONF_DRV_12MA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* GPIO CTRL Bit Definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OWL_GPIO_CTLR_PENDING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OWL_GPIO_CTLR_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OWL_GPIO_CTLR_SAMPLE_CLK_24M 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* GPIO TYPE Bit Definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OWL_GPIO_INT_LEVEL_HIGH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OWL_GPIO_INT_LEVEL_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OWL_GPIO_INT_EDGE_RISING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OWL_GPIO_INT_EDGE_FALLING 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OWL_GPIO_INT_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * struct owl_pullctl - Actions pad pull control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @reg: offset to the pull control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @shift: shift value of the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @width: width of the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct owl_pullctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * struct owl_st - Actions pad schmitt trigger enable register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @reg: offset to the schmitt trigger enable register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @shift: shift value of the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @width: width of the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct owl_st {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * struct owl_pingroup - Actions pingroup definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @name: name of the pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @pads: list of pins assigned to this pingroup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @npads: size of @pads array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @funcs: list of pinmux functions for this pingroup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @nfuncs: size of @funcs array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @mfpctl_reg: multiplexing control register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @mfpctl_shift: multiplexing control register bit mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @mfpctl_width: multiplexing control register width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @drv_reg: drive control register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @drv_shift: drive control register bit mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @drv_width: driver control register width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @sr_reg: slew rate control register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @sr_shift: slew rate control register bit mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @sr_width: slew rate control register width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct owl_pingroup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int *pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int npads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned int nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int mfpctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int mfpctl_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int mfpctl_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int drv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int drv_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int drv_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int sr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int sr_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int sr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * struct owl_padinfo - Actions pinctrl pad info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @pad: pad name of the SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @pullctl: pull control register info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @st: schmitt trigger register info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct owl_padinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct owl_pullctl *pullctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct owl_st *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * struct owl_pinmux_func - Actions pinctrl mux functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @name: name of the pinmux function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @groups: array of pin groups that may select this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @ngroups: number of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct owl_pinmux_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * struct owl_gpio_port - Actions GPIO port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @offset: offset of the GPIO port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @pins: number of pins belongs to the GPIO port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @outen: offset of the output enable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @inen: offset of the input enable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @dat: offset of the data register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @intc_ctl: offset of the interrupt control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @intc_pd: offset of the interrupt pending register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @intc_msk: offset of the interrupt mask register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @intc_type: offset of the interrupt type register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct owl_gpio_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int outen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int inen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int intc_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int intc_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int intc_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int intc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 shared_ctl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * struct owl_pinctrl_soc_data - Actions pin controller driver configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * @pins: array describing all pins of the pin controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * @npins: number of entries in @pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @functions: array describing all mux functions of this SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * @nfunction: number of entries in @functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @groups: array describing all pin groups of this SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @ngroups: number of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @padinfo: array describing the pad info of this SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @ngpios: number of pingroups the driver should expose as GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @ports: array describing all GPIO ports of this SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @nports: number of GPIO ports in this SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct owl_pinctrl_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) const struct owl_pinmux_func *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) const struct owl_pingroup *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) const struct owl_padinfo *padinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) const struct owl_gpio_port *ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int (*padctl_val2arg)(const struct owl_padinfo *padinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int (*padctl_arg2val)(const struct owl_padinfo *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int owl_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct owl_pinctrl_soc_data *soc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #endif /* __PINCTRL_OWL_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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