^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OWL SoC's Pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: David Liu <liuwei@actions-semi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "pinctrl-owl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * struct owl_pinctrl - pinctrl state of the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @dev: device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @pctrldev: pinctrl handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @chip: gpio chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @lock: spinlock to protect registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @clk: clock control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @soc: reference to soc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @base: pinctrl register base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @irq_chip: IRQ chip information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @num_irq: number of possible interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @irq: interrupt numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct owl_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct pinctrl_dev *pctrldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const struct owl_pinctrl_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int num_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) reg_val = readl_relaxed(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) reg_val = (reg_val & ~mask) | (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writel_relaxed(reg_val, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 bit, u32 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 tmp, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) tmp = readl_relaxed(pctrl->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mask = (1 << width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return (tmp >> bit) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 bit, u32 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mask = (1 << width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mask = mask << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) owl_update_bits(pctrl->base + reg, mask, (arg << bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return pctrl->soc->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return pctrl->soc->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *pins = pctrl->soc->groups[group].pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *num_pins = pctrl->soc->groups[group].npads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) seq_printf(s, "%s", dev_name(pctrl->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct pinctrl_ops owl_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .get_groups_count = owl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .get_group_name = owl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .get_group_pins = owl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .pin_dbg_show = owl_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return pctrl->soc->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return pctrl->soc->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *groups = pctrl->soc->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *num_groups = pctrl->soc->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 option_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 option_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) for (id = 0; id < g->nfuncs; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (g->funcs[id] == function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (WARN_ON(id == g->nfuncs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) option_num = (1 << g->mfpctl_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (id > option_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) id -= option_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) option_mask = option_num - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *mask = (option_mask << g->mfpctl_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *val = (id << g->mfpctl_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int owl_set_mux(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) const struct owl_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) g = &pctrl->soc->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (get_group_mfp_mask_val(g, function, &mask, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct pinmux_ops owl_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .get_functions_count = owl_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .get_function_name = owl_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .get_function_groups = owl_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .set_mux = owl_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 *bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 *width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case PIN_CONFIG_BIAS_BUS_HOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!info->pullctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *reg = info->pullctl->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *bit = info->pullctl->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *width = info->pullctl->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!info->st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *reg = info->st->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *bit = info->st->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) *width = info->st->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) const struct owl_padinfo *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 reg, bit, width, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) info = &pctrl->soc->padinfo[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) arg = owl_read_field(pctrl, reg, bit, width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!pctrl->soc->padctl_val2arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = pctrl->soc->padctl_val2arg(info, param, &arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) const struct owl_padinfo *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 reg, bit, width, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) info = &pctrl->soc->padinfo[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!pctrl->soc->padctl_arg2val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = pctrl->soc->padctl_arg2val(info, param, &arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) owl_write_field(pctrl, reg, arg, bit, width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int owl_group_pinconf_reg(const struct owl_pingroup *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 *bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 *width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (g->drv_reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *reg = g->drv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *bit = g->drv_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) *width = g->drv_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (g->sr_reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *reg = g->sr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *bit = g->sr_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *width = g->sr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned int param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) switch (*arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *arg = OWL_PINCONF_DRV_2MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *arg = OWL_PINCONF_DRV_4MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *arg = OWL_PINCONF_DRV_8MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *arg = OWL_PINCONF_DRV_12MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (*arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *arg = OWL_PINCONF_SLEW_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *arg = OWL_PINCONF_SLEW_SLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) switch (*arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case OWL_PINCONF_DRV_2MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) *arg = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case OWL_PINCONF_DRV_4MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *arg = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case OWL_PINCONF_DRV_8MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) *arg = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case OWL_PINCONF_DRV_12MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) *arg = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (*arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) *arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) *arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int owl_group_config_get(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) const struct owl_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 reg, bit, width, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) g = &pctrl->soc->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) arg = owl_read_field(pctrl, reg, bit, width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = owl_group_pinconf_val2arg(g, param, &arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int owl_group_config_set(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) const struct owl_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 reg, bit, width, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) g = &pctrl->soc->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = owl_group_pinconf_arg2val(g, param, &arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Update register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) owl_write_field(pctrl, reg, arg, bit, width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const struct pinconf_ops owl_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .pin_config_get = owl_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .pin_config_set = owl_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .pin_config_group_get = owl_group_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .pin_config_group_set = owl_group_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static struct pinctrl_desc owl_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .pctlops = &owl_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .pmxops = &owl_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .confops = &owl_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const struct owl_gpio_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned int start = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) for (i = 0; i < pctrl->soc->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) const struct owl_gpio_port *port = &pctrl->soc->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (*pin >= start && *pin < start + port->pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) *pin -= start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) start += port->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) val = readl_relaxed(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) val |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) val &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) writel_relaxed(val, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) const struct owl_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) port = owl_gpio_get_port(pctrl, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (WARN_ON(port == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) gpio_base = pctrl->base + port->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * GPIOs have higher priority over other modules, so either setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * them as OUT or IN is sufficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) owl_gpio_update_reg(gpio_base + port->outen, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) const struct owl_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) port = owl_gpio_get_port(pctrl, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (WARN_ON(port == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) gpio_base = pctrl->base + port->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* disable gpio output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) owl_gpio_update_reg(gpio_base + port->outen, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* disable gpio input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) owl_gpio_update_reg(gpio_base + port->inen, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) const struct owl_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) port = owl_gpio_get_port(pctrl, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (WARN_ON(port == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) gpio_base = pctrl->base + port->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) val = readl_relaxed(gpio_base + port->dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return !!(val & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) const struct owl_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) port = owl_gpio_get_port(pctrl, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (WARN_ON(port == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) gpio_base = pctrl->base + port->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) owl_gpio_update_reg(gpio_base + port->dat, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) const struct owl_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) port = owl_gpio_get_port(pctrl, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (WARN_ON(port == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) gpio_base = pctrl->base + port->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) owl_gpio_update_reg(gpio_base + port->outen, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) owl_gpio_update_reg(gpio_base + port->inen, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int owl_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) const struct owl_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) port = owl_gpio_get_port(pctrl, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (WARN_ON(port == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) gpio_base = pctrl->base + port->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) owl_gpio_update_reg(gpio_base + port->inen, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) owl_gpio_update_reg(gpio_base + port->outen, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) owl_gpio_update_reg(gpio_base + port->dat, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) const struct owl_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) unsigned int offset, value, irq_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * Since the hardware doesn't support interrupts on both edges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * emulate it in the software by setting the single edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * interrupt and switching to the opposite edge while ACKing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (owl_gpio_get(&pctrl->chip, gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) irq_type = OWL_GPIO_INT_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) irq_type = OWL_GPIO_INT_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) irq_type = OWL_GPIO_INT_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) irq_type = OWL_GPIO_INT_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) irq_type = OWL_GPIO_INT_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) irq_type = OWL_GPIO_INT_LEVEL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) port = owl_gpio_get_port(pctrl, &gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (WARN_ON(port == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) gpio_base = pctrl->base + port->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) offset = (gpio < 16) ? 4 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) value = readl_relaxed(gpio_base + port->intc_type + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) value |= irq_type << ((gpio % 16) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) writel_relaxed(value, gpio_base + port->intc_type + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static void owl_gpio_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) const struct owl_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned int gpio = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) port = owl_gpio_get_port(pctrl, &gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (WARN_ON(port == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) gpio_base = pctrl->base + port->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* disable port interrupt if no interrupt pending bit is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) val = readl_relaxed(gpio_base + port->intc_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) owl_gpio_update_reg(gpio_base + port->intc_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static void owl_gpio_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) const struct owl_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) unsigned int gpio = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) port = owl_gpio_get_port(pctrl, &gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (WARN_ON(port == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) gpio_base = pctrl->base + port->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* enable port interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) value = readl_relaxed(gpio_base + port->intc_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) << port->shared_ctl_offset * 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) writel_relaxed(value, gpio_base + port->intc_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* enable GPIO interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static void owl_gpio_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) const struct owl_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned int gpio = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * Switch the interrupt edge to the opposite edge of the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * which got triggered for the case of emulating both edges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (owl_gpio_get(gc, gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) port = owl_gpio_get_port(pctrl, &gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (WARN_ON(port == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) gpio_base = pctrl->base + port->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) owl_gpio_update_reg(gpio_base + port->intc_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) irq_set_type(pctrl, data->hwirq, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static void owl_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct irq_domain *domain = pctrl->chip.irq.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) unsigned int parent = irq_desc_get_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) const struct owl_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) unsigned int pin, irq, offset = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) unsigned long pending_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) for (i = 0; i < pctrl->soc->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) port = &pctrl->soc->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) base = pctrl->base + port->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* skip ports that are not associated with this irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (parent != pctrl->irq[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) goto skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pending_irq = readl_relaxed(base + port->intc_pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) for_each_set_bit(pin, &pending_irq, port->pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) irq = irq_find_mapping(domain, offset + pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* clear pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) owl_gpio_update_reg(base + port->intc_pd, pin, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) skip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) offset += port->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static int owl_gpio_init(struct owl_pinctrl *pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct gpio_irq_chip *gpio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int ret, i, j, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) chip = &pctrl->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) chip->ngpio = pctrl->soc->ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) chip->label = dev_name(pctrl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) chip->parent = pctrl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) chip->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) chip->of_node = pctrl->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) pctrl->irq_chip.name = chip->of_node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) gpio_irq = &chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) gpio_irq->chip = &pctrl->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) gpio_irq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) gpio_irq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) gpio_irq->parent_handler = owl_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) gpio_irq->parent_handler_data = pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) gpio_irq->num_parents = pctrl->num_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) gpio_irq->parents = pctrl->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) sizeof(*gpio_irq->map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!gpio_irq->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) const struct owl_gpio_port *port = &pctrl->soc->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) for (j = 0; j < port->pins; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) gpio_irq->map[offset + j] = gpio_irq->parents[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) offset += port->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ret = gpiochip_add_data(&pctrl->chip, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_err(pctrl->dev, "failed to register gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int owl_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct owl_pinctrl_soc_data *soc_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct owl_pinctrl *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) pctrl->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (IS_ERR(pctrl->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return PTR_ERR(pctrl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* enable GPIO/MFP clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) pctrl->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (IS_ERR(pctrl->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_err(&pdev->dev, "no clock defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return PTR_ERR(pctrl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret = clk_prepare_enable(pctrl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dev_err(&pdev->dev, "clk enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) raw_spin_lock_init(&pctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) owl_pinctrl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) owl_pinctrl_desc.pins = soc_data->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) owl_pinctrl_desc.npins = soc_data->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) pctrl->chip.direction_input = owl_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) pctrl->chip.direction_output = owl_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) pctrl->chip.get = owl_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) pctrl->chip.set = owl_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pctrl->chip.request = owl_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) pctrl->chip.free = owl_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) pctrl->soc = soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) pctrl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) &owl_pinctrl_desc, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (IS_ERR(pctrl->pctrldev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ret = PTR_ERR(pctrl->pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ret = platform_irq_count(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) pctrl->num_irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) sizeof(*pctrl->irq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (!pctrl->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) for (i = 0; i < pctrl->num_irq ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ret = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) pctrl->irq[i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ret = owl_gpio_init(pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) platform_set_drvdata(pdev, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) err_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) clk_disable_unprepare(pctrl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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