^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) # PHY drivers for Xilinx platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) config PHY_XILINX_ZYNQMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) tristate "Xilinx ZynqMP PHY driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) depends on ARCH_ZYNQMP || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) select GENERIC_PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Enable this to support ZynqMP High Speed Gigabit Transceiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) that is part of ZynqMP SoC.