^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004-2007 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contact: Felipe Balbi <felipe.balbi@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Current status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * - HS USB ULPI mode works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * - 3-pin mode support may be added in future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/usb/musb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/usb/ulpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mfd/twl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCPC_CTRL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCPC_CTRL_RTSOL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCPC_CTRL_EXTSWR (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCPC_CTRL_EXTSWC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCPC_CTRL_VOICESW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCPC_CTRL_OUT64K (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCPC_CTRL_RTSCTSSW (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCPC_CTRL_HS_UART (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCPC_IO_CTRL 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCPC_IO_CTRL_MICBIASEN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MCPC_IO_CTRL_CTS_NPU (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MCPC_IO_CTRL_RXD_PU (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MCPC_IO_CTRL_TXDTYP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCPC_IO_CTRL_CTSTYP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCPC_IO_CTRL_RTSTYP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCPC_CTRL2 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OTHER_FUNC_CTRL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OTHER_IFC_CTRL 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OTHER_INT_EN_RISE 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OTHER_INT_EN_FALL 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OTHER_INT_STS 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OTHER_INT_LATCH 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OTHER_INT_VB_SESS_VLD (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OTHER_INT_MANU (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OTHER_INT_ABNORMAL_STRESS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ID_STATUS 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ID_RES_FLOAT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ID_RES_440K (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ID_RES_200K (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ID_RES_102K (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ID_RES_GND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define POWER_CTRL 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define POWER_CTRL_OTG_ENAB (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OTHER_IFC_CTRL2 0xAF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define REG_CTRL_EN 0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define REG_CTRL_ERROR 0xB5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ULPI_I2C_CONFLICT_INTEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OTHER_FUNC_CTRL2 0xB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* following registers do not have separate _clr and _set registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VBUS_DEBOUNCE 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ID_DEBOUNCE 0xC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VBAT_TIMER 0xD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PHY_PWR_CTRL 0xFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PHY_PWR_PHYPWD (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PHY_CLK_CTRL 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define REQ_PHY_DPLL_CLK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PHY_CLK_CTRL_STS 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PHY_DPLL_CLK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* In module TWL_MODULE_PM_MASTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define STS_HW_CONDITIONS 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* In module TWL_MODULE_PM_RECEIVER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VUSB_DEDICATED1 0x7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VUSB_DEDICATED2 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VUSB1V5_DEV_GRP 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VUSB1V5_TYPE 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VUSB1V5_REMAP 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VUSB1V8_DEV_GRP 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VUSB1V8_TYPE 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VUSB1V8_REMAP 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VUSB3V1_DEV_GRP 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VUSB3V1_TYPE 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VUSB3V1_REMAP 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* In module TWL4030_MODULE_INTBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PMBR1 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static irqreturn_t twl4030_usb_irq(int irq, void *_twl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * If VBUS is valid or ID is ground, then we know a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * cable is present and we need to be runtime-enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline bool cable_present(enum musb_vbus_id_status stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return stat == MUSB_VBUS_VALID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) stat == MUSB_ID_GROUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct twl4030_usb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct usb_phy phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* TWL4030 internal USB regulator supplies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct regulator *usb1v5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct regulator *usb1v8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct regulator *usb3v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* for vbus reporting with irqs disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* pin configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) enum twl4030_usb_mode usb_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum musb_vbus_id_status linkstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) atomic_t connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bool vbus_supplied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool musb_mailbox_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct delayed_work id_workaround_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* internal define on top of container_of */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define phy_to_twl(x) container_of((x), struct twl4030_usb, phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 module, u8 data, u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 check = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if ((twl_i2c_write_u8(module, data, address) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) (twl_i2c_read_u8(module, &check, address) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) (check == data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 1, module, address, check, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Failed once: Try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if ((twl_i2c_write_u8(module, data, address) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) (twl_i2c_read_u8(module, &check, address) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (check == data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 2, module, address, check, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Failed again: Return error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define twl4030_usb_write_verify(twl, address, data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static inline int twl4030_usb_write(struct twl4030_usb *twl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 address, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_dbg(twl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = twl_i2c_read_u8(module, &data, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_dbg(twl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "TWL4030:readb[0x%x,0x%x] Error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) module, address, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return twl4030_readb(twl, TWL_MODULE_USB, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return twl4030_usb_write(twl, ULPI_SET(reg), bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret < 0 || !(ret & PHY_DPLL_CLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * if clocks are off, registers are not updated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * but we can assume we don't drive VBUS in this case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static enum musb_vbus_id_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) twl4030_usb_linkstat(struct twl4030_usb *twl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) enum musb_vbus_id_status linkstat = MUSB_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) twl->vbus_supplied = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * For ID/VBUS sensing, see manual section 15.4.8 ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * except when using only battery backup power, two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * comparators produce VBUS_PRES and ID_PRES signals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * which don't match docs elsewhere. But ... BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * and BIT(2) of STS_HW_CONDITIONS, respectively, do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * seem to match up. If either is true the USB_PRES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * signal is active, the OTG module is activated, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * its interrupt may be raised (may wake the system).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_err(twl->dev, "USB link status err %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) else if (status & (BIT(7) | BIT(2))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (status & BIT(7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (twl4030_is_driving_vbus(twl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) status &= ~BIT(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) twl->vbus_supplied = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (status & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) linkstat = MUSB_ID_GROUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else if (status & BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) linkstat = MUSB_VBUS_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) linkstat = MUSB_VBUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (twl->linkstat != MUSB_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) linkstat = MUSB_VBUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) kobject_uevent(&twl->dev->kobj, linkstat == MUSB_VBUS_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ? KOBJ_ONLINE : KOBJ_OFFLINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) status, status, linkstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* REVISIT this assumes host and peripheral controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * are registered, and that both are active...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return linkstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) twl->usb_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case T2_USB_MODE_ULPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ULPI_IFC_CTRL_CARKITMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ULPI_FUNC_CTRL_XCVRSEL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ULPI_FUNC_CTRL_OPMODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case -1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* FIXME: power on defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (val >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* enable DPLL to access PHY registers over I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) val |= REQ_PHY_DPLL_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) (u8)val) < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) timeout = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PHY_DPLL_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) && time_before(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PHY_DPLL_CLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(twl->dev, "Timeout setting T2 HSUSB "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "PHY DPLL clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* let ULPI control the DPLL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) val &= ~REQ_PHY_DPLL_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) (u8)val) < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pwr &= ~PHY_PWR_PHYPWD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pwr |= PHY_PWR_PHYPWD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int __maybe_unused twl4030_usb_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct twl4030_usb *twl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * we need enabled runtime on resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * so turn irq off here, so we do not get it early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * note: wakeup on usb plug works independently of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_dbg(twl->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) disable_irq(twl->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int __maybe_unused twl4030_usb_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct twl4030_usb *twl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_dbg(twl->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enable_irq(twl->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* check whether cable status changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) twl4030_usb_irq(0, twl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int __maybe_unused twl4030_usb_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct twl4030_usb *twl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_dbg(twl->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) __twl4030_phy_power(twl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) regulator_disable(twl->usb1v5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) regulator_disable(twl->usb1v8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) regulator_disable(twl->usb3v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int __maybe_unused twl4030_usb_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct twl4030_usb *twl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_dbg(twl->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) res = regulator_enable(twl->usb3v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_err(twl->dev, "Failed to enable usb3v1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) res = regulator_enable(twl->usb1v8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(twl->dev, "Failed to enable usb1v8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * in twl4030) resets the VUSB_DEDICATED2 register. This reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * SLEEP. We work around this by clearing the bit after usv3v1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * is re-activated. This ensures that VUSB3V1 is really active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) res = regulator_enable(twl->usb1v5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_err(twl->dev, "Failed to enable usb1v5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) __twl4030_phy_power(twl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) twl4030_usb_write(twl, PHY_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) twl4030_usb_read(twl, PHY_CLK_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) (PHY_CLK_CTRL_CLOCKGATING_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PHY_CLK_CTRL_CLK32K_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) twl4030_i2c_access(twl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) twl4030_usb_set_mode(twl, twl->usb_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (twl->usb_mode == T2_USB_MODE_ULPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) twl4030_i2c_access(twl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * According to the TPS65950 TRM, there has to be at least 50ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * delay between setting POWER_CTRL_OTG_ENAB and enabling charging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * so wait here so that a fully enabled phy can be expected after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int twl4030_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct twl4030_usb *twl = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_dbg(twl->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int twl4030_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct twl4030_usb *twl = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_dbg(twl->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pm_runtime_get_sync(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) schedule_delayed_work(&twl->id_workaround_work, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pm_runtime_mark_last_busy(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pm_runtime_put_autosuspend(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Enable writing to power configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* input to VUSB3V1 LDO is from VBAT, not VBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Initialize 3.1V regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (IS_ERR(twl->usb3v1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Initialize 1.5V regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (IS_ERR(twl->usb1v5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Initialize 1.8V regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (IS_ERR(twl->usb1v8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* disable access to power configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static ssize_t twl4030_usb_vbus_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct twl4030_usb *twl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mutex_lock(&twl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ret = sprintf(buf, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) twl->vbus_supplied ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) mutex_unlock(&twl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct twl4030_usb *twl = _twl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) enum musb_vbus_id_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) status = twl4030_usb_linkstat(twl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mutex_lock(&twl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) twl->linkstat = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mutex_unlock(&twl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (cable_present(status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (atomic_add_unless(&twl->connected, 1, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_dbg(twl->dev, "%s: cable connected %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pm_runtime_get_sync(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) twl->musb_mailbox_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (atomic_add_unless(&twl->connected, -1, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_dbg(twl->dev, "%s: cable disconnected %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pm_runtime_mark_last_busy(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pm_runtime_put_autosuspend(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) twl->musb_mailbox_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (twl->musb_mailbox_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) err = musb_mailbox(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) twl->musb_mailbox_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* don't schedule during sleep - irq works right then */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (status == MUSB_ID_GROUND && pm_runtime_active(twl->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) cancel_delayed_work(&twl->id_workaround_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) schedule_delayed_work(&twl->id_workaround_work, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) sysfs_notify(&twl->dev->kobj, NULL, "vbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static void twl4030_id_workaround_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) id_workaround_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) twl4030_usb_irq(0, twl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int twl4030_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct twl4030_usb *twl = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pm_runtime_get_sync(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) twl->linkstat = MUSB_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) schedule_delayed_work(&twl->id_workaround_work, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pm_runtime_mark_last_busy(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pm_runtime_put_autosuspend(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int twl4030_set_peripheral(struct usb_otg *otg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) otg->gadget = gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (!gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) otg->state = OTG_STATE_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) otg->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) otg->state = OTG_STATE_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const struct phy_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .init = twl4030_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .power_on = twl4030_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .power_off = twl4030_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const struct dev_pm_ops twl4030_usb_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) SET_RUNTIME_PM_OPS(twl4030_usb_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) twl4030_usb_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SET_SYSTEM_SLEEP_PM_OPS(twl4030_usb_suspend, twl4030_usb_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int twl4030_usb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct twl4030_usb *twl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int status, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct usb_otg *otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!twl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) of_property_read_u32(np, "usb_mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) (enum twl4030_usb_mode *)&twl->usb_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) else if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) twl->usb_mode = pdata->usb_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (!otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) twl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) twl->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) twl->vbus_supplied = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) twl->linkstat = MUSB_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) twl->musb_mailbox_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) twl->phy.dev = twl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) twl->phy.label = "twl4030";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) twl->phy.otg = otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) twl->phy.type = USB_PHY_TYPE_USB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) otg->usb_phy = &twl->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) otg->set_host = twl4030_set_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) otg->set_peripheral = twl4030_set_peripheral;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) phy = devm_phy_create(twl->dev, NULL, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_dbg(&pdev->dev, "Failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) phy_set_drvdata(phy, twl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) phy_provider = devm_of_phy_provider_register(twl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (IS_ERR(phy_provider))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* init mutex for workqueue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mutex_init(&twl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) err = twl4030_usb_ldo_init(twl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_err(&pdev->dev, "ldo init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) usb_add_phy_dev(&twl->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) platform_set_drvdata(pdev, twl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (device_create_file(&pdev->dev, &dev_attr_vbus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_warn(&pdev->dev, "could not create sysfs file\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Our job is to use irqs and status from the power module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * to keep the transceiver disabled when nothing's connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * FIXME we actually shouldn't start enabling it until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * USB controller drivers have said they're ready, by calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * set_host() and/or set_peripheral() ... OTG_capable boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * need both handles, otherwise just one suffices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) twl4030_usb_irq, IRQF_TRIGGER_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) twl->irq, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) err = phy_create_lookup(phy, "usb", "musb-hdrc.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pm_runtime_mark_last_busy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pm_runtime_put_autosuspend(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static int twl4030_usb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct twl4030_usb *twl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) usb_remove_phy(&twl->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pm_runtime_get_sync(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) cancel_delayed_work_sync(&twl->id_workaround_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) device_remove_file(twl->dev, &dev_attr_vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* set transceiver mode to power on defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) twl4030_usb_set_mode(twl, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* idle ulpi before powering off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (cable_present(twl->linkstat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) pm_runtime_put_noidle(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) pm_runtime_mark_last_busy(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) pm_runtime_put_sync(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pm_runtime_disable(twl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* autogate 60MHz ULPI clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * clear dpll clock request for i2c access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * disable 32KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) val = twl4030_usb_read(twl, PHY_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (val >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) val |= PHY_CLK_CTRL_CLOCKGATING_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* disable complete OTG block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static const struct of_device_id twl4030_usb_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) { .compatible = "ti,twl4030-usb" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static struct platform_driver twl4030_usb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .probe = twl4030_usb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .remove = twl4030_usb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .name = "twl4030_usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .pm = &twl4030_usb_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .of_match_table = of_match_ptr(twl4030_usb_id_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static int __init twl4030_usb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return platform_driver_register(&twl4030_usb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) subsys_initcall(twl4030_usb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static void __exit twl4030_usb_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) platform_driver_unregister(&twl4030_usb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) module_exit(twl4030_usb_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) MODULE_ALIAS("platform:twl4030_usb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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