^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * phy-ti-pipe3 - PIPE3 PHY driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Kishon Vijay Abraham I <kishon@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/phy/omap_control_phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_STATUS 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL_GO 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLL_CONFIGURATION1 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLL_CONFIGURATION2 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PLL_CONFIGURATION3 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLL_CONFIGURATION4 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PLL_REGM_MASK 0x001FFE00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PLL_REGM_SHIFT 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PLL_REGM_F_MASK 0x0003FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PLL_REGM_F_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PLL_REGN_MASK 0x000001FE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLL_REGN_SHIFT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PLL_SELFREQDCO_MASK 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PLL_SELFREQDCO_SHIFT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PLL_SD_MASK 0x0003FC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PLL_SD_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SET_PLL_GO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PLL_LDOPWDN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PLL_TICOPWDN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PLL_LOCK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PLL_IDLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SATA_PLL_SOFT_RESET BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCIE_PCS_MASK 0xFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCIE_PCS_DELAY_COUNT_SHIFT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define INTERFACE_MASK GENMASK(31, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define INTERFACE_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define INTERFACE_MODE_USBSS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define INTERFACE_MODE_SATA_1P5 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define INTERFACE_MODE_SATA_3P0 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define INTERFACE_MODE_PCIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LOSD_MASK GENMASK(17, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LOSD_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MEM_PLLDIV GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PIPE3_PHY_RX_TRIM 0x0000001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MEM_DLL_TRIM_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PIPE3_PHY_RX_DLL 0x00000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MEM_DLL_PHINT_RATE_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MEM_HS_RATE_MASK GENMASK(28, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MEM_HS_RATE_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MEM_OVRD_HS_RATE BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MEM_OVRD_HS_RATE_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MEM_CDR_FASTLOCK BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MEM_CDR_FASTLOCK_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MEM_CDR_LBW_MASK GENMASK(22, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MEM_CDR_LBW_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MEM_CDR_STEPCNT_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MEM_CDR_STL_MASK GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MEM_CDR_STL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MEM_CDR_THR_MASK GENMASK(15, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MEM_CDR_THR_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MEM_CDR_THR_MODE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MEM_CDR_THR_MODE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MEM_CDR_2NDO_SDM_MODE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PIPE3_PHY_RX_EQUALIZER 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MEM_EQLEV_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MEM_EQLEV_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MEM_EQFTC_MASK GENMASK(15, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MEM_EQFTC_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MEM_EQCTL_MASK GENMASK(10, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MEM_EQCTL_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MEM_OVRD_EQLEV BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MEM_OVRD_EQLEV_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MEM_OVRD_EQFTC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MEM_OVRD_EQFTC_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MEM_CDR_LOS_SOURCE_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * This is an Empirical value that works, need to confirm the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PLL_IDLE_TIME 100 /* in milliseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PLL_LOCK_TIME 100 /* in milliseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum pipe3_mode { PIPE3_MODE_PCIE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PIPE3_MODE_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PIPE3_MODE_USBSS };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct pipe3_dpll_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 freq:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct pipe3_dpll_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct pipe3_dpll_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct pipe3_settings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 ana_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 ana_losd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 dig_fastlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 dig_lbw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 dig_stepcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 dig_stl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u8 dig_thr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 dig_thr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 dig_2ndo_sdm_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 dig_hs_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 dig_ovrd_hs_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 dll_trim_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 dll_phint_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 eq_lev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 eq_ftc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 eq_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 eq_ovrd_lev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 eq_ovrd_ftc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct ti_pipe3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void __iomem *pll_ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void __iomem *phy_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void __iomem *phy_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct device *control_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct clk *wkupclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct clk *sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct clk *refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct clk *div_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct pipe3_dpll_map *dpll_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct regmap *phy_power_syscon; /* ctrl. reg. acces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct regmap *pcs_syscon; /* ctrl. reg. acces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int dpll_reset_reg; /* reg. index within syscon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int power_reg; /* power reg. index within syscon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bool sata_refclk_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) enum pipe3_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct pipe3_settings settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static struct pipe3_dpll_map dpll_map_usb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { }, /* Terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct pipe3_dpll_map dpll_map_sata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { }, /* Terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct pipe3_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) enum pipe3_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct pipe3_dpll_map *dpll_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct pipe3_settings settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct pipe3_data data_usb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .mode = PIPE3_MODE_USBSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .dpll_map = dpll_map_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .settings = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .ana_interface = INTERFACE_MODE_USBSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .ana_losd = 0xa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .dig_fastlock = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .dig_lbw = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .dig_stepcnt = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .dig_stl = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .dig_thr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .dig_thr_mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .dig_2ndo_sdm_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .dig_hs_rate = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .dig_ovrd_hs_rate = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .dll_trim_sel = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .dll_phint_rate = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .eq_lev = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .eq_ftc = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .eq_ctl = 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .eq_ovrd_lev = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .eq_ovrd_ftc = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct pipe3_data data_sata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .mode = PIPE3_MODE_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .dpll_map = dpll_map_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .settings = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .ana_interface = INTERFACE_MODE_SATA_3P0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .ana_losd = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .dig_fastlock = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .dig_lbw = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .dig_stepcnt = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .dig_stl = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .dig_thr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .dig_thr_mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .dig_2ndo_sdm_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .dig_hs_rate = 0, /* Not in TRM preferred settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .dll_trim_sel = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .eq_lev = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .eq_ftc = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .eq_ctl = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .eq_ovrd_lev = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .eq_ovrd_ftc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct pipe3_data data_pcie = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .mode = PIPE3_MODE_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .settings = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .ana_interface = INTERFACE_MODE_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .ana_losd = 0xa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .dig_fastlock = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .dig_lbw = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .dig_stepcnt = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .dig_stl = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .dig_thr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .dig_thr_mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .dig_2ndo_sdm_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .dig_hs_rate = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .dig_ovrd_hs_rate = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .dll_trim_sel = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .dll_phint_rate = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .eq_lev = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .eq_ftc = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .eq_ctl = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .eq_ovrd_lev = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .eq_ovrd_ftc = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return __raw_readl(addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) __raw_writel(data, addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct pipe3_dpll_map *dpll_map = phy->dpll_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) rate = clk_get_rate(phy->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) for (; dpll_map->rate; dpll_map++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (rate == dpll_map->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return &dpll_map->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int ti_pipe3_power_off(struct phy *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct ti_pipe3 *phy = phy_get_drvdata(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!phy->phy_power_syscon) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) omap_control_phy_power(phy->control_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PIPE3_PHY_PWRCTL_CLK_CMD_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void ti_pipe3_calibrate(struct ti_pipe3 *phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int ti_pipe3_power_on(struct phy *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct ti_pipe3 *phy = phy_get_drvdata(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) bool rx_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!phy->phy_power_syscon) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) omap_control_phy_power(phy->control_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rate = clk_get_rate(phy->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(phy->dev, "Invalid clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) rate = rate / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) val = rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * For PCIe, TX and RX must be powered on simultaneously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * For USB and SATA, TX must be powered on before RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (phy->mode == PIPE3_MODE_SATA || phy->mode == PIPE3_MODE_USBSS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val = PIPE3_PHY_TX_POWERON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) rx_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (rx_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (phy->mode == PIPE3_MODE_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ti_pipe3_calibrate(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (val & PLL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } while (!time_after(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(phy->dev, "DPLL failed to lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct pipe3_dpll_params *dpll_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dpll_params = ti_pipe3_get_dpll_params(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!dpll_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) val &= ~PLL_REGN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) val |= dpll_params->n << PLL_REGN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) val &= ~PLL_SELFREQDCO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) val &= ~PLL_REGM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) val |= dpll_params->m << PLL_REGM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) val &= ~PLL_REGM_F_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) val |= dpll_params->mf << PLL_REGM_F_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) val &= ~PLL_SD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) val |= dpll_params->sd << PLL_SD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ti_pipe3_dpll_wait_lock(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void ti_pipe3_calibrate(struct ti_pipe3 *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct pipe3_settings *s = &phy->settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) s->dig_lbw << MEM_CDR_LBW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) s->dig_stl << MEM_CDR_STL_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) s->dig_thr << MEM_CDR_THR_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) val &= ~MEM_DLL_TRIM_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) val &= ~MEM_DLL_PHINT_RATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) val |= s->eq_lev << MEM_EQLEV_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) s->eq_ftc << MEM_EQFTC_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) s->eq_ctl << MEM_EQCTL_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (phy->mode == PIPE3_MODE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) val = ti_pipe3_readl(phy->phy_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) val &= ~MEM_CDR_LOS_SOURCE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int ti_pipe3_init(struct phy *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct ti_pipe3 *phy = phy_get_drvdata(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ti_pipe3_enable_clocks(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Set pcie_pcs register to 0x96 for proper functioning of phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * 18-1804.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (phy->mode == PIPE3_MODE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!phy->pcs_syscon) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) omap_control_pcie_pcs(phy->control_dev, 0x96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PCIE_PCS_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Bring it out of IDLE if it is IDLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (val & PLL_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) val &= ~PLL_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = ti_pipe3_dpll_wait_lock(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* SATA has issues if re-programmed when locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Program the DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = ti_pipe3_dpll_program(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ti_pipe3_disable_clocks(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ti_pipe3_calibrate(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int ti_pipe3_exit(struct phy *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct ti_pipe3 *phy = phy_get_drvdata(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* If dpll_reset_syscon is not present we wont power down SATA DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * due to Errata i783
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* PCIe doesn't have internal DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (phy->mode != PIPE3_MODE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Put DPLL in IDLE mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) val |= PLL_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* wait for LDO and Oscillator to power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } while (!time_after(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* i783: SATA needs control bit toggle after PLL unlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (phy->mode == PIPE3_MODE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) SATA_PLL_SOFT_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ti_pipe3_disable_clocks(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const struct phy_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .init = ti_pipe3_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .exit = ti_pipe3_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .power_on = ti_pipe3_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .power_off = ti_pipe3_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const struct of_device_id ti_pipe3_id_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct device *dev = phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) phy->refclk = devm_clk_get(dev, "refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (IS_ERR(phy->refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_err(dev, "unable to get refclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* older DTBs have missing refclk in SATA PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * so don't bail out in case of SATA PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (phy->mode != PIPE3_MODE_SATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return PTR_ERR(phy->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (phy->mode != PIPE3_MODE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) phy->wkupclk = devm_clk_get(dev, "wkupclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (IS_ERR(phy->wkupclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_err(dev, "unable to get wkupclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return PTR_ERR(phy->wkupclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) phy->wkupclk = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) phy->sys_clk = devm_clk_get(dev, "sysclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (IS_ERR(phy->sys_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_err(dev, "unable to get sysclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (phy->mode == PIPE3_MODE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) clk = devm_clk_get(dev, "dpll_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_err(dev, "unable to get dpll ref clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) clk_set_rate(clk, 1500000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) clk = devm_clk_get(dev, "dpll_ref_m2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dev_err(dev, "unable to get dpll ref m2 clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) clk_set_rate(clk, 100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) clk = devm_clk_get(dev, "phy-div");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_err(dev, "unable to get phy-div clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) clk_set_rate(clk, 100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) phy->div_clk = devm_clk_get(dev, "div-clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (IS_ERR(phy->div_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_err(dev, "unable to get div-clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return PTR_ERR(phy->div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) phy->div_clk = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct device *dev = phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct device_node *control_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct platform_device *control_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "syscon-phy-power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (IS_ERR(phy->phy_power_syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "can't get syscon-phy-power, using control device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) phy->phy_power_syscon = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (of_property_read_u32_index(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "syscon-phy-power", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) &phy->power_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(dev, "couldn't get power reg. offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (!phy->phy_power_syscon) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) control_node = of_parse_phandle(node, "ctrl-module", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (!control_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_err(dev, "Failed to get control device phandle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) control_pdev = of_find_device_by_node(control_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!control_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(dev, "Failed to get control device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) phy->control_dev = &control_pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (phy->mode == PIPE3_MODE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "syscon-pcs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (IS_ERR(phy->pcs_syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "can't get syscon-pcs, using omap control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) phy->pcs_syscon = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (of_property_read_u32_index(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "syscon-pcs", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) &phy->pcie_pcs_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "couldn't get pcie pcs reg. offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (phy->mode == PIPE3_MODE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) "syscon-pllreset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (IS_ERR(phy->dpll_reset_syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) "can't get syscon-pllreset, sata dpll won't idle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) phy->dpll_reset_syscon = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (of_property_read_u32_index(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) "syscon-pllreset", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) &phy->dpll_reset_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "couldn't get pllreset reg. offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct device *dev = phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "phy_rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) phy->phy_rx = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (IS_ERR(phy->phy_rx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return PTR_ERR(phy->phy_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "phy_tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) phy->phy_tx = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return PTR_ERR_OR_ZERO(phy->phy_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct device *dev = phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (phy->mode == PIPE3_MODE_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "pll_ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) phy->pll_ctrl_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return PTR_ERR_OR_ZERO(phy->pll_ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int ti_pipe3_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct ti_pipe3 *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct pipe3_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) match = of_match_device(ti_pipe3_id_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) data = (struct pipe3_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_err(dev, "no driver data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) phy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) phy->mode = data->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) phy->dpll_map = data->dpll_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) phy->settings = data->settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = ti_pipe3_get_pll_base(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = ti_pipe3_get_tx_rx_base(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ret = ti_pipe3_get_sysctrl(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ret = ti_pipe3_get_clk(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) platform_set_drvdata(pdev, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * Prevent auto-disable of refclk for SATA PHY due to Errata i783
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (phy->mode == PIPE3_MODE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (!IS_ERR(phy->refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) clk_prepare_enable(phy->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) phy->sata_refclk_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) generic_phy = devm_phy_create(dev, NULL, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (IS_ERR(generic_phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return PTR_ERR(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) phy_set_drvdata(generic_phy, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ti_pipe3_power_off(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int ti_pipe3_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct ti_pipe3 *phy = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (phy->mode == PIPE3_MODE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) clk_disable_unprepare(phy->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) phy->sata_refclk_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (!IS_ERR(phy->refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = clk_prepare_enable(phy->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!IS_ERR(phy->wkupclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ret = clk_prepare_enable(phy->wkupclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) goto disable_refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (!IS_ERR(phy->div_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = clk_prepare_enable(phy->div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) goto disable_wkupclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) disable_wkupclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!IS_ERR(phy->wkupclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) clk_disable_unprepare(phy->wkupclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) disable_refclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (!IS_ERR(phy->refclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) clk_disable_unprepare(phy->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (!IS_ERR(phy->wkupclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) clk_disable_unprepare(phy->wkupclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!IS_ERR(phy->refclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) clk_disable_unprepare(phy->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!IS_ERR(phy->div_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) clk_disable_unprepare(phy->div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const struct of_device_id ti_pipe3_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .compatible = "ti,phy-usb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .data = &data_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .compatible = "ti,omap-usb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .data = &data_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .compatible = "ti,phy-pipe3-sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .data = &data_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .compatible = "ti,phy-pipe3-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .data = &data_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static struct platform_driver ti_pipe3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .probe = ti_pipe3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .remove = ti_pipe3_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .name = "ti-pipe3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .of_match_table = ti_pipe3_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) module_platform_driver(ti_pipe3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) MODULE_ALIAS("platform:ti_pipe3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) MODULE_AUTHOR("Texas Instruments Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) MODULE_DESCRIPTION("TI PIPE3 phy driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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