^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * omap-control-phy.c - The PHY part of control module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Kishon Vijay Abraham I <kishon@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy/omap_control_phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * omap_control_pcie_pcs - set the PCS delay count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @dev: the control module device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @delay: 8 bit delay value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void omap_control_pcie_pcs(struct device *dev, u8 delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct omap_control_phy *control_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (IS_ERR(dev) || !dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) pr_err("%s: invalid device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) control_phy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (!control_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) dev_err(dev, "%s: invalid control phy device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) dev_err(dev, "%s: unsupported operation\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) val = readl(control_phy->pcie_pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) writel(val, control_phy->pcie_pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * omap_control_phy_power - power on/off the phy using control module reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @dev: the control module device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @on: 0 or 1, based on powering on or off the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void omap_control_phy_power(struct device *dev, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct omap_control_phy *control_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (IS_ERR(dev) || !dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pr_err("%s: invalid device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) control_phy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!control_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dev_err(dev, "%s: invalid control phy device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) val = readl(control_phy->power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) switch (control_phy->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case OMAP_CTRL_TYPE_USB2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) val &= ~OMAP_CTRL_DEV_PHY_PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) val |= OMAP_CTRL_DEV_PHY_PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case OMAP_CTRL_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case OMAP_CTRL_TYPE_PIPE3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rate = clk_get_rate(control_phy->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) rate = rate/1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) val |= rate <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case OMAP_CTRL_TYPE_DRA7USB2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val &= ~OMAP_CTRL_USB2_PHY_PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val |= OMAP_CTRL_USB2_PHY_PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case OMAP_CTRL_TYPE_AM437USB2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val &= ~(AM437X_CTRL_USB2_PHY_PD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) AM437X_CTRL_USB2_OTG_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val |= (AM437X_CTRL_USB2_OTGVDET_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) AM437X_CTRL_USB2_OTGSESSEND_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) AM437X_CTRL_USB2_OTGSESSEND_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val |= (AM437X_CTRL_USB2_PHY_PD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AM437X_CTRL_USB2_OTG_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_err(dev, "%s: type %d not recognized\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __func__, control_phy->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(val, control_phy->power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) EXPORT_SYMBOL_GPL(omap_control_phy_power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @ctrl_phy: struct omap_control_phy *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Writes to the mailbox register to notify the usb core that a usb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * device has been connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val = readl(ctrl_phy->otghs_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writel(val, ctrl_phy->otghs_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * impedance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @ctrl_phy: struct omap_control_phy *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Writes to the mailbox register to notify the usb core that it has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * connected to a usb host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val = readl(ctrl_phy->otghs_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val &= ~OMAP_CTRL_DEV_SESSEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) OMAP_CTRL_DEV_VBUSVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writel(val, ctrl_phy->otghs_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * impedance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @ctrl_phy: struct omap_control_phy *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Writes to the mailbox register to notify the usb core it's now in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * disconnected state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) val = readl(ctrl_phy->otghs_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(val, ctrl_phy->otghs_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * or device mode or to denote disconnected state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @dev: the control module device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @mode: The mode to which usb should be configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * This is an API to write to the mailbox register to notify the usb core that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * a usb device has been connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void omap_control_usb_set_mode(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) enum omap_control_usb_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct omap_control_phy *ctrl_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (IS_ERR(dev) || !dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ctrl_phy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!ctrl_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_err(dev, "Invalid control phy device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case USB_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) omap_control_usb_host_mode(ctrl_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case USB_MODE_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) omap_control_usb_device_mode(ctrl_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case USB_MODE_DISCONNECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) omap_control_usb_set_sessionend(ctrl_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_vdbg(dev, "invalid omap control usb mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const enum omap_control_phy_type am437usb2_data = OMAP_CTRL_TYPE_AM437USB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct of_device_id omap_control_phy_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .compatible = "ti,control-phy-otghs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .data = &otghs_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .compatible = "ti,control-phy-usb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .data = &usb2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .compatible = "ti,control-phy-pipe3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .data = &pipe3_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .compatible = "ti,control-phy-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .data = &pcie_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .compatible = "ti,control-phy-usb2-dra7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .data = &dra7usb2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .compatible = "ti,control-phy-usb2-am437",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .data = &am437usb2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int omap_control_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct omap_control_phy *control_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) of_id = of_match_device(omap_control_phy_id_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!control_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) control_phy->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) control_phy->type = *(enum omap_control_phy_type *)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "otghs_control");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) control_phy->otghs_control = devm_ioremap_resource(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) &pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (IS_ERR(control_phy->otghs_control))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return PTR_ERR(control_phy->otghs_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) control_phy->power = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (IS_ERR(control_phy->power)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_err(&pdev->dev, "Couldn't get power register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return PTR_ERR(control_phy->power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (control_phy->type == OMAP_CTRL_TYPE_PIPE3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) control_phy->type == OMAP_CTRL_TYPE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) control_phy->sys_clk = devm_clk_get(control_phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "sys_clkin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (IS_ERR(control_phy->sys_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pr_err("%s: unable to get sys_clkin\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (control_phy->type == OMAP_CTRL_TYPE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "pcie_pcs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) control_phy->pcie_pcs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (IS_ERR(control_phy->pcie_pcs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return PTR_ERR(control_phy->pcie_pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_set_drvdata(control_phy->dev, control_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct platform_driver omap_control_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .probe = omap_control_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "omap-control-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .of_match_table = omap_control_phy_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int __init omap_control_phy_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return platform_driver_register(&omap_control_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) subsys_initcall(omap_control_phy_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void __exit omap_control_phy_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) platform_driver_unregister(&omap_control_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) module_exit(omap_control_phy_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_ALIAS("platform:omap_control_phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MODULE_AUTHOR("Texas Instruments Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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