^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Texas Instruments CPSW Port's PHY Interface Mode selection Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on cpsw-phy-sel.c driver created by Mugunthan V N <mugunthanvnm@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* AM33xx SoC specific definitions for the CONTROL port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AM33XX_GMII_SEL_MODE_MII 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AM33XX_GMII_SEL_MODE_RMII 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AM33XX_GMII_SEL_MODE_RGMII 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PHY_GMII_SEL_PORT_MODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PHY_GMII_SEL_RGMII_ID_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PHY_GMII_SEL_RMII_IO_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PHY_GMII_SEL_LAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct phy_gmii_sel_phy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct phy_gmii_sel_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct phy *if_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int rmii_clock_external;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int phy_if_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct regmap_field *fields[PHY_GMII_SEL_LAST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct phy_gmii_sel_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const struct reg_field (*regfields)[PHY_GMII_SEL_LAST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) bool use_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct phy_gmii_sel_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const struct phy_gmii_sel_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct phy_gmii_sel_phy_priv *if_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct phy_gmii_sel_phy_priv *if_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct device *dev = if_phy->priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct regmap_field *regfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int ret, rgmii_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 gmii_sel_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (mode != PHY_MODE_ETHERNET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) switch (submode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case PHY_INTERFACE_MODE_RMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) gmii_sel_mode = AM33XX_GMII_SEL_MODE_RMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case PHY_INTERFACE_MODE_RGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case PHY_INTERFACE_MODE_RGMII_RXID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case PHY_INTERFACE_MODE_RGMII_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case PHY_INTERFACE_MODE_RGMII_TXID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) rgmii_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case PHY_INTERFACE_MODE_MII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case PHY_INTERFACE_MODE_GMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev_warn(dev, "port%u: unsupported mode: \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if_phy->id, phy_modes(submode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if_phy->phy_if_mode = submode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __func__, if_phy->id, submode, rgmii_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if_phy->rmii_clock_external);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = regmap_field_write(regfield, gmii_sel_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_err(dev, "port%u: set mode fail %d", if_phy->id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) regfield = if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = regmap_field_write(regfield, rgmii_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) regfield = if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = regmap_field_write(regfield,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if_phy->rmii_clock_external);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct reg_field phy_gmii_sel_fields_am33xx[][PHY_GMII_SEL_LAST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am33xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .num_ports = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) BIT(PHY_GMII_SEL_RMII_IO_CLK_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .regfields = phy_gmii_sel_fields_am33xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct reg_field phy_gmii_sel_fields_dra7[][PHY_GMII_SEL_LAST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dra7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .num_ports = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .regfields = phy_gmii_sel_fields_dra7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .num_ports = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .regfields = phy_gmii_sel_fields_am33xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct reg_field phy_gmii_sel_fields_am654[][PHY_GMII_SEL_LAST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .use_of_data = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .regfields = phy_gmii_sel_fields_am654,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct of_device_id phy_gmii_sel_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .compatible = "ti,am3352-phy-gmii-sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .data = &phy_gmii_sel_soc_am33xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .compatible = "ti,dra7xx-phy-gmii-sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .data = &phy_gmii_sel_soc_dra7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .compatible = "ti,am43xx-phy-gmii-sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .data = &phy_gmii_sel_soc_am33xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .compatible = "ti,dm814-phy-gmii-sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .data = &phy_gmii_sel_soc_dm814,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .compatible = "ti,am654-phy-gmii-sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .data = &phy_gmii_sel_soc_am654,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct phy_ops phy_gmii_sel_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .set_mode = phy_gmii_sel_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct phy *phy_gmii_sel_of_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct phy_gmii_sel_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int phy_id = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (args->args_count < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!priv || !priv->if_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) args->args_count < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (phy_id > priv->num_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (phy_id != priv->if_phys[phy_id - 1].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) phy_id--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) priv->if_phys[phy_id].rmii_clock_external = args->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_dbg(dev, "%s id:%u ext:%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) priv->if_phys[phy_id].id, args->args[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return priv->if_phys[phy_id].if_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int phy_gmii_init_phy(struct phy_gmii_sel_priv *priv, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct phy_gmii_sel_phy_priv *if_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) const struct reg_field *fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct regmap_field *regfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct reg_field field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if_phy->id = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if_phy->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) fields = soc_data->regfields[port - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) field = *fields++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) field.reg += priv->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_dbg(dev, "%s field %x %d %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) field.reg, field.msb, field.lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) regfield = devm_regmap_field_alloc(dev, priv->regmap, field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (IS_ERR(regfield))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return PTR_ERR(regfield);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if_phy->fields[PHY_GMII_SEL_PORT_MODE] = regfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) field = *fields++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) field.reg += priv->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) regfield = devm_regmap_field_alloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) priv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (IS_ERR(regfield))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return PTR_ERR(regfield);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE] = regfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_dbg(dev, "%s field %x %d %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) field.reg, field.msb, field.lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) field = *fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) field.reg += priv->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) regfield = devm_regmap_field_alloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) priv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (IS_ERR(regfield))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return PTR_ERR(regfield);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN] = regfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_dbg(dev, "%s field %x %d %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) field.reg, field.msb, field.lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if_phy->if_phy = devm_phy_create(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) priv->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) &phy_gmii_sel_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (IS_ERR(if_phy->if_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = PTR_ERR(if_phy->if_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_err(dev, "Failed to create phy%d %d\n", port, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) phy_set_drvdata(if_phy->if_phy, if_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int phy_gmii_sel_init_ports(struct phy_gmii_sel_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct phy_gmii_sel_phy_priv *if_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (soc_data->use_of_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) const __be32 *offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) offset = of_get_address(dev->of_node, 0, &size, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) priv->num_ports = size / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!priv->num_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) priv->reg_offset = __be32_to_cpu(*offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if_phys = devm_kcalloc(dev, priv->num_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) sizeof(*if_phys), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!if_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_dbg(dev, "%s %d\n", __func__, priv->num_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) for (i = 0; i < priv->num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = phy_gmii_init_phy(priv, i + 1, &if_phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) priv->if_phys = if_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int phy_gmii_sel_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct phy_gmii_sel_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) of_id = of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) priv->soc_data = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) priv->num_ports = priv->soc_data->num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) priv->regmap = syscon_node_to_regmap(node->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (IS_ERR(priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_err(dev, "Failed to get syscon %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = phy_gmii_sel_init_ports(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_set_drvdata(&pdev->dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) priv->phy_provider =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) devm_of_phy_provider_register(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) phy_gmii_sel_of_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (IS_ERR(priv->phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = PTR_ERR(priv->phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_err(dev, "Failed to create phy provider %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct platform_driver phy_gmii_sel_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .probe = phy_gmii_sel_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .name = "phy-gmii-sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .of_match_table = phy_gmii_sel_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) module_platform_driver(phy_gmii_sel_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MODULE_DESCRIPTION("TI CPSW Port's PHY Interface Mode selection Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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