^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2015, Google Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __PHY_TEGRA_XUSB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __PHY_TEGRA_XUSB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/usb/role.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* legacy entry points for backwards-compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct tegra_xusb_lane_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const char * const *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int num_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct tegra_xusb_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const struct tegra_xusb_lane_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct tegra_xusb_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct tegra_xusb_usb3_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct tegra_xusb_lane base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline struct tegra_xusb_usb3_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) to_usb3_lane(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return container_of(lane, struct tegra_xusb_usb3_lane, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct tegra_xusb_usb2_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct tegra_xusb_lane base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 hs_curr_level_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bool powered_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline struct tegra_xusb_usb2_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) to_usb2_lane(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return container_of(lane, struct tegra_xusb_usb2_lane, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct tegra_xusb_ulpi_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tegra_xusb_lane base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline struct tegra_xusb_ulpi_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) to_ulpi_lane(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return container_of(lane, struct tegra_xusb_ulpi_lane, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct tegra_xusb_hsic_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct tegra_xusb_lane base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 strobe_trim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 rx_strobe_trim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 rx_data_trim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 tx_rtune_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 tx_rtune_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 tx_rslew_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 tx_rslew_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bool auto_term;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline struct tegra_xusb_hsic_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) to_hsic_lane(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return container_of(lane, struct tegra_xusb_hsic_lane, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct tegra_xusb_pcie_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct tegra_xusb_lane base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline struct tegra_xusb_pcie_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) to_pcie_lane(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return container_of(lane, struct tegra_xusb_pcie_lane, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct tegra_xusb_sata_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct tegra_xusb_lane base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline struct tegra_xusb_sata_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) to_sata_lane(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return container_of(lane, struct tegra_xusb_sata_lane, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct tegra_xusb_lane_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct tegra_xusb_lane *(*probe)(struct tegra_xusb_pad *pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void (*remove)(struct tegra_xusb_lane *lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * pads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct tegra_xusb_pad_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct tegra_xusb_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct tegra_xusb_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct tegra_xusb_pad *(*probe)(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct tegra_xusb_pad_soc *soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void (*remove)(struct tegra_xusb_pad *pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct tegra_xusb_pad_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const struct tegra_xusb_lane_soc *lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct tegra_xusb_pad_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct tegra_xusb_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct tegra_xusb_pad_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct tegra_xusb_padctl *padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct phy **lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const struct tegra_xusb_lane_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline struct tegra_xusb_pad *to_tegra_xusb_pad(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return container_of(dev, struct tegra_xusb_pad, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int tegra_xusb_pad_init(struct tegra_xusb_pad *pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int tegra_xusb_pad_register(struct tegra_xusb_pad *pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const struct phy_ops *ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void tegra_xusb_pad_unregister(struct tegra_xusb_pad *pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct tegra_xusb_usb3_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct tegra_xusb_pad base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static inline struct tegra_xusb_usb3_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) to_usb3_pad(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return container_of(pad, struct tegra_xusb_usb3_pad, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct tegra_xusb_usb2_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct tegra_xusb_pad base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline struct tegra_xusb_usb2_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) to_usb2_pad(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return container_of(pad, struct tegra_xusb_usb2_pad, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct tegra_xusb_ulpi_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct tegra_xusb_pad base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static inline struct tegra_xusb_ulpi_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) to_ulpi_pad(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return container_of(pad, struct tegra_xusb_ulpi_pad, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct tegra_xusb_hsic_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct tegra_xusb_pad base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct regulator *supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static inline struct tegra_xusb_hsic_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) to_hsic_pad(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return container_of(pad, struct tegra_xusb_hsic_pad, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct tegra_xusb_pcie_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct tegra_xusb_pad base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct clk *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline struct tegra_xusb_pcie_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) to_pcie_pad(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return container_of(pad, struct tegra_xusb_pcie_pad, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct tegra_xusb_sata_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct tegra_xusb_pad base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct clk *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline struct tegra_xusb_sata_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) to_sata_pad(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return container_of(pad, struct tegra_xusb_sata_pad, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct tegra_xusb_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct tegra_xusb_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct tegra_xusb_padctl *padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct tegra_xusb_lane *lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct usb_role_switch *usb_role_sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct work_struct usb_phy_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct usb_phy usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) const struct tegra_xusb_port_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static inline struct tegra_xusb_port *to_tegra_xusb_port(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return container_of(dev, struct tegra_xusb_port, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct tegra_xusb_lane_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const char *type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const char *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) tegra_xusb_port_find_lane(struct tegra_xusb_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) const struct tegra_xusb_lane_map *map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) const char *function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct tegra_xusb_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tegra_xusb_find_port(struct tegra_xusb_padctl *padctl, const char *type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct tegra_xusb_usb2_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct tegra_xusb_port base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct regulator *supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) enum usb_dr_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bool internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int usb3_port_fake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static inline struct tegra_xusb_usb2_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) to_usb2_port(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return container_of(port, struct tegra_xusb_usb2_port, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct tegra_xusb_usb2_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tegra_xusb_find_usb2_port(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) void tegra_xusb_usb2_port_release(struct tegra_xusb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) void tegra_xusb_usb2_port_remove(struct tegra_xusb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct tegra_xusb_ulpi_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct tegra_xusb_port base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct regulator *supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bool internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static inline struct tegra_xusb_ulpi_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) to_ulpi_port(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return container_of(port, struct tegra_xusb_ulpi_port, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void tegra_xusb_ulpi_port_release(struct tegra_xusb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct tegra_xusb_hsic_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct tegra_xusb_port base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static inline struct tegra_xusb_hsic_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) to_hsic_port(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return container_of(port, struct tegra_xusb_hsic_port, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void tegra_xusb_hsic_port_release(struct tegra_xusb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct tegra_xusb_usb3_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct tegra_xusb_port base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct regulator *supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) bool context_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) bool internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) bool disable_gen2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 tap1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 amp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 ctle_z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 ctle_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static inline struct tegra_xusb_usb3_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) to_usb3_port(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return container_of(port, struct tegra_xusb_usb3_port, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct tegra_xusb_usb3_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) tegra_xusb_find_usb3_port(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) void tegra_xusb_usb3_port_release(struct tegra_xusb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) void tegra_xusb_usb3_port_remove(struct tegra_xusb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct tegra_xusb_port_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) void (*release)(struct tegra_xusb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) void (*remove)(struct tegra_xusb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int (*enable)(struct tegra_xusb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) void (*disable)(struct tegra_xusb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct tegra_xusb_lane *(*map)(struct tegra_xusb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * pad controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct tegra_xusb_padctl_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct tegra_xusb_padctl_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct tegra_xusb_padctl *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) (*probe)(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) const struct tegra_xusb_padctl_soc *soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) void (*remove)(struct tegra_xusb_padctl *padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int (*usb3_save_context)(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int (*hsic_set_idle)(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int index, bool idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int (*usb3_set_lfps_detect)(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int index, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int (*vbus_override)(struct tegra_xusb_padctl *padctl, bool set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int (*utmi_port_reset)(struct phy *phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct tegra_xusb_padctl_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) const struct tegra_xusb_pad_soc * const *pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int num_pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) const struct tegra_xusb_port_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) } usb2, ulpi, hsic, usb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) } ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) const struct tegra_xusb_padctl_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) const char * const *supply_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned int num_supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) bool supports_gen2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) bool need_fake_usb3_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct tegra_xusb_padctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) const struct tegra_xusb_padctl_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct tegra_xusb_pad *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct tegra_xusb_pad *sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct tegra_xusb_pad *ulpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct tegra_xusb_pad *usb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct tegra_xusb_pad *hsic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct list_head ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct list_head lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct list_head pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct regulator_bulk_data *supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_dbg(padctl->dev, "%08lx < %08x\n", offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) writel(value, padctl->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 value = readl(padctl->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_dbg(padctl->dev, "%08lx > %08x\n", offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct tegra_xusb_lane *tegra_xusb_find_lane(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) extern const struct tegra_xusb_padctl_soc tegra124_xusb_padctl_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #if defined(CONFIG_ARCH_TEGRA_210_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) extern const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #if defined(CONFIG_ARCH_TEGRA_186_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #if defined(CONFIG_ARCH_TEGRA_194_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #endif /* __PHY_TEGRA_XUSB_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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