^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "xusb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* FUSE USB_CALIB registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HS_CURR_LEVEL_PAD_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HS_TERM_RANGE_ADJ_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HS_TERM_RANGE_ADJ_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HS_SQUELCH_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HS_SQUELCH_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RPD_CTRL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RPD_CTRL_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* XUSB PADCTL registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XUSB_PADCTL_USB2_PAD_MUX 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define USB2_PORT_SHIFT(x) ((x) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define USB2_PORT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PORT_XUSB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HSIC_PORT_SHIFT(x) ((x) + 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HSIC_PORT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PORT_HSIC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XUSB_PADCTL_USB2_PORT_CAP 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XUSB_PADCTL_SS_PORT_CAP 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PORTX_CAP_SHIFT(x) ((x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PORT_CAP_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PORT_CAP_DISABLED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PORT_CAP_HOST 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PORT_CAP_DEVICE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PORT_CAP_OTG 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define XUSB_PADCTL_ELPG_PROGRAM 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ALL_WAKE_EVENTS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) USB2_HSIC_PORT_WAKEUP_EVENT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define XUSB_PADCTL_ELPG_PROGRAM_1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define XUSB_PADCTL_SS_PORT_CFG 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PORTX_SPEED_SUPPORT_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PORT_SPEED_SUPPORT_GEN1 (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HS_CURR_LEVEL(x) ((x) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TERM_SEL BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define USB2_OTG_PD BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define USB2_OTG_PD2 BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define USB2_OTG_PD2_OVRD_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define USB2_OTG_PD_ZI BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define USB2_OTG_PD_DR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RPD_CTRL(x) (((x) & 0x1f) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BIAS_PAD_PD BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define USB2_PD_TRK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HSIC_PD_TX_DATA0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HSIC_PD_TX_STROBE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HSIC_PD_RX_DATA0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HSIC_PD_RX_STROBE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HSIC_PD_ZI_DATA0 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HSIC_PD_ZI_STROBE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HSIC_RPD_DATA0 BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HSIC_RPD_STROBE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HSIC_RPU_DATA0 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HSIC_RPU_STROBE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HSIC_PD_TRK BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define USB2_VBUS_ID 0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VBUS_OVERRIDE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ID_OVERRIDE(x) (((x) & 0xf) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ID_OVERRIDE_FLOATING ID_OVERRIDE(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .offset = _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .funcs = tegra186_##_type##_functions, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct tegra_xusb_fuse_calibration {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 *hs_curr_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 hs_squelch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 hs_term_range_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 rpd_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct tegra186_xusb_padctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct tegra_xusb_padctl base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct tegra_xusb_fuse_calibration calib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* UTMI bias and tracking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct clk *usb2_trk_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int bias_pad_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline struct tegra186_xusb_padctl *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return container_of(padctl, struct tegra186_xusb_padctl, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* USB 2.0 UTMI PHY support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct tegra_xusb_usb2_lane *usb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!usb2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) INIT_LIST_HEAD(&usb2->base.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) usb2->base.soc = &pad->soc->lanes[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) usb2->base.index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) usb2->base.pad = pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) usb2->base.np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) err = tegra_xusb_lane_parse_dt(&usb2->base, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) kfree(usb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return &usb2->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) kfree(usb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .probe = tegra186_usb2_lane_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .remove = tegra186_usb2_lane_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct device *dev = padctl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mutex_lock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (priv->bias_pad_enable++ > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) err = clk_prepare_enable(priv->usb2_trk_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) value &= ~USB2_TRK_START_TIMER(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) value |= USB2_TRK_START_TIMER(0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) value |= USB2_TRK_DONE_RESET_TIMER(0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) value &= ~BIAS_PAD_PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) value &= ~HS_SQUELCH_LEVEL(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) value &= ~USB2_PD_TRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mutex_lock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (WARN_ON(priv->bias_pad_enable == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (--priv->bias_pad_enable > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) value |= USB2_PD_TRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) clk_disable_unprepare(priv->usb2_trk_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct tegra_xusb_usb2_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct device *dev = padctl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int index = lane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) port = tegra_xusb_find_usb2_port(padctl, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(dev, "no port found for USB2 lane %u\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) tegra186_utmi_bias_pad_power_on(padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) value &= ~USB2_OTG_PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) value &= ~USB2_OTG_PD_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int index = lane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) value |= USB2_OTG_PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) value |= USB2_OTG_PD_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) tegra186_utmi_bias_pad_power_off(padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) bool status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) value = padctl_readl(padctl, USB2_VBUS_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) value |= VBUS_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) value &= ~ID_OVERRIDE(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) value |= ID_OVERRIDE_FLOATING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) value &= ~VBUS_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) padctl_writel(padctl, value, USB2_VBUS_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bool status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) value = padctl_readl(padctl, USB2_VBUS_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (value & VBUS_OVERRIDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) value &= ~VBUS_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) padctl_writel(padctl, value, USB2_VBUS_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) value = padctl_readl(padctl, USB2_VBUS_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) value &= ~ID_OVERRIDE(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) value |= ID_OVERRIDE_GROUNDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) value &= ~ID_OVERRIDE(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) value |= ID_OVERRIDE_FLOATING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) padctl_writel(padctl, value, USB2_VBUS_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) lane->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mutex_lock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (mode == PHY_MODE_USB_OTG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (submode == USB_ROLE_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) tegra186_xusb_padctl_id_override(padctl, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) err = regulator_enable(port->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) } else if (submode == USB_ROLE_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) tegra186_xusb_padctl_vbus_override(padctl, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) } else if (submode == USB_ROLE_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * When port is peripheral only or role transitions to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (regulator_is_enabled(port->supply))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) regulator_disable(port->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) tegra186_xusb_padctl_id_override(padctl, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) tegra186_xusb_padctl_vbus_override(padctl, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int tegra186_utmi_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct tegra_xusb_usb2_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int index = lane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct device *dev = padctl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) port = tegra_xusb_find_usb2_port(padctl, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_err(dev, "no port found for USB2 lane %u\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (port->mode == USB_DR_MODE_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) else if (port->mode == USB_DR_MODE_PERIPHERAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) else if (port->mode == USB_DR_MODE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) else if (port->mode == USB_DR_MODE_OTG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) value &= ~USB2_OTG_PD_ZI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) value |= TERM_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) value &= ~HS_CURR_LEVEL(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (usb2->hs_curr_level_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int hs_current_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) hs_current_level = (int)priv->calib.hs_curr_level[index] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) usb2->hs_curr_level_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (hs_current_level < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) hs_current_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (hs_current_level > 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hs_current_level = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) value |= HS_CURR_LEVEL(hs_current_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) value &= ~TERM_RANGE_ADJ(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) value &= ~RPD_CTRL(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) value |= RPD_CTRL(priv->calib.rpd_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* TODO: pad power saving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) tegra_phy_xusb_utmi_pad_power_on(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int tegra186_utmi_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* TODO: pad power saving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) tegra_phy_xusb_utmi_pad_power_down(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int tegra186_utmi_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct tegra_xusb_usb2_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int index = lane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct device *dev = padctl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) port = tegra_xusb_find_usb2_port(padctl, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(dev, "no port found for USB2 lane %u\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (port->supply && port->mode == USB_DR_MODE_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) err = regulator_enable(port->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(dev, "failed to enable port %u VBUS: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) index, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int tegra186_utmi_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct tegra_xusb_usb2_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned int index = lane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct device *dev = padctl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) port = tegra_xusb_find_usb2_port(padctl, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (!port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_err(dev, "no port found for USB2 lane %u\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (port->supply && port->mode == USB_DR_MODE_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) err = regulator_disable(port->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(dev, "failed to disable port %u VBUS: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) index, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct phy_ops utmi_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .init = tegra186_utmi_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .exit = tegra186_utmi_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .power_on = tegra186_utmi_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .power_off = tegra186_utmi_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .set_mode = tegra186_utmi_phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static struct tegra_xusb_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) const struct tegra_xusb_pad_soc *soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct tegra_xusb_usb2_pad *usb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct tegra_xusb_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!usb2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pad = &usb2->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pad->ops = &tegra186_usb2_lane_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pad->soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) err = tegra_xusb_pad_init(pad, padctl, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) kfree(usb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (IS_ERR(priv->usb2_trk_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) err = PTR_ERR(priv->usb2_trk_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) err = tegra_xusb_pad_register(pad, &utmi_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_set_drvdata(&pad->dev, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) device_unregister(&pad->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) kfree(usb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .probe = tegra186_usb2_pad_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .remove = tegra186_usb2_pad_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const char * const tegra186_usb2_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) "xusb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) tegra186_usb2_port_map(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .release = tegra_xusb_usb2_port_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .remove = tegra_xusb_usb2_port_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .enable = tegra186_usb2_port_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .disable = tegra186_usb2_port_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .map = tegra186_usb2_port_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* SuperSpeed PHY support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct tegra_xusb_usb3_lane *usb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (!usb3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) INIT_LIST_HEAD(&usb3->base.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) usb3->base.soc = &pad->soc->lanes[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) usb3->base.index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) usb3->base.pad = pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) usb3->base.np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) err = tegra_xusb_lane_parse_dt(&usb3->base, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) kfree(usb3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return &usb3->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) kfree(usb3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .probe = tegra186_usb3_lane_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .remove = tegra186_usb3_lane_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) tegra186_usb3_port_map(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .release = tegra_xusb_usb3_port_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .remove = tegra_xusb_usb3_port_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .enable = tegra186_usb3_port_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .disable = tegra186_usb3_port_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .map = tegra186_usb3_port_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static int tegra186_usb3_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct tegra_xusb_usb3_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct tegra_xusb_usb2_port *usb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) unsigned int index = lane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct device *dev = padctl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) port = tegra_xusb_find_usb3_port(padctl, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_err(dev, "no port found for USB3 lane %u\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!usb2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_err(dev, "no companion port found for USB3 lane %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) mutex_lock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (usb2->mode == USB_DR_MODE_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) else if (usb2->mode == USB_DR_MODE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) else if (usb2->mode == USB_DR_MODE_OTG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (padctl->soc->supports_gen2 && port->disable_gen2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) value &= ~(PORTX_SPEED_SUPPORT_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PORTX_SPEED_SUPPORT_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) value |= (PORT_SPEED_SUPPORT_GEN1 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PORTX_SPEED_SUPPORT_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) value &= ~SSPX_ELPG_VCORE_DOWN(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) value &= ~SSPX_ELPG_CLAMP_EN(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int tegra186_usb3_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct tegra_xusb_usb3_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) unsigned int index = lane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct device *dev = padctl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) port = tegra_xusb_find_usb3_port(padctl, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (!port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_err(dev, "no port found for USB3 lane %u\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) mutex_lock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) value |= SSPX_ELPG_CLAMP_EN(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) usleep_range(250, 350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) value |= SSPX_ELPG_VCORE_DOWN(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int tegra186_usb3_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int tegra186_usb3_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const struct phy_ops usb3_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .init = tegra186_usb3_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .exit = tegra186_usb3_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .power_on = tegra186_usb3_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .power_off = tegra186_usb3_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static struct tegra_xusb_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) const struct tegra_xusb_pad_soc *soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct tegra_xusb_usb3_pad *usb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct tegra_xusb_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!usb3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) pad = &usb3->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) pad->ops = &tegra186_usb3_lane_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) pad->soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) err = tegra_xusb_pad_init(pad, padctl, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) kfree(usb3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) err = tegra_xusb_pad_register(pad, &usb3_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_set_drvdata(&pad->dev, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) device_unregister(&pad->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) kfree(usb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .probe = tegra186_usb3_pad_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .remove = tegra186_usb3_pad_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const char * const tegra186_usb3_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) "xusb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct device *dev = padctl->base.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) unsigned int i, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u32 value, *level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) count = padctl->base.soc->ports.usb2.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (err != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_err(dev, "failed to read calibration fuse: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) HS_CURR_LEVEL_PAD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) padctl->calib.hs_curr_level = level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) HS_SQUELCH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) HS_TERM_RANGE_ADJ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_err(dev, "failed to read calibration fuse: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static struct tegra_xusb_padctl *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) tegra186_xusb_padctl_probe(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) const struct tegra_xusb_padctl_soc *soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct tegra186_xusb_padctl *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) priv->base.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) priv->base.soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) err = tegra186_xusb_read_fuse_calibration(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return &priv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .probe = tegra186_xusb_padctl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .remove = tegra186_xusb_padctl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .vbus_override = tegra186_xusb_padctl_vbus_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const char * const tegra186_xusb_padctl_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) "avdd-pll-erefeut",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) "avdd-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) "vclamp-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) "vddio-hsic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .name = "usb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .lanes = tegra186_usb2_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .ops = &tegra186_usb2_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .name = "usb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .lanes = tegra186_usb3_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .ops = &tegra186_usb3_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) &tegra186_usb2_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) &tegra186_usb3_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #if 0 /* TODO implement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) &tegra186_hsic_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .num_pads = ARRAY_SIZE(tegra186_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .pads = tegra186_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .ports = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .usb2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .ops = &tegra186_usb2_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #if 0 /* TODO implement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .hsic = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .ops = &tegra186_hsic_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .usb3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .ops = &tegra186_usb3_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .ops = &tegra186_xusb_padctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .supply_names = tegra186_xusb_padctl_supply_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static const char * const tegra194_xusb_padctl_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) "avdd-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "vclamp-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) TEGRA186_LANE("usb2-3", 0, 0, 0, usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .name = "usb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .lanes = tegra194_usb2_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .ops = &tegra186_usb2_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) TEGRA186_LANE("usb3-3", 0, 0, 0, usb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .name = "usb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .lanes = tegra194_usb3_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .ops = &tegra186_usb3_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) &tegra194_usb2_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) &tegra194_usb3_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .num_pads = ARRAY_SIZE(tegra194_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .pads = tegra194_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .ports = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .usb2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .ops = &tegra186_usb2_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .count = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .usb3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .ops = &tegra186_usb3_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .count = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .ops = &tegra186_xusb_padctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .supply_names = tegra194_xusb_padctl_supply_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .supports_gen2 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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