^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mailbox_client.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "xusb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? 15 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FUSE_SKU_CALIB_HS_IREF_CAP_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FUSE_SKU_CALIB_HS_IREF_CAP_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FUSE_SKU_CALIB_HS_SQUELCH_LEVEL_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FUSE_SKU_CALIB_HS_SQUELCH_LEVEL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XUSB_PADCTL_USB2_PORT_CAP 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_SHIFT(x) ((x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XUSB_PADCTL_USB2_PORT_CAP_PORT_CAP_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XUSB_PADCTL_USB2_PORT_CAP_DISABLED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XUSB_PADCTL_USB2_PORT_CAP_HOST 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define XUSB_PADCTL_USB2_PORT_CAP_DEVICE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XUSB_PADCTL_USB2_PORT_CAP_OTG 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XUSB_PADCTL_SS_PORT_MAP 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XUSB_PADCTL_SS_PORT_MAP_PORT_MAP_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN_EARLY(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (1 << (17 + (x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define XUSB_PADCTL_IOPHY_USB3_PADX_CTL2(x) (0x058 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_CDR_CNTL_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_CDR_CNTL_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_CDR_CNTL_VAL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_Z_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_Z_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_G_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_G_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_VAL 0xf070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_WANDER_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_WANDER_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_WANDER_VAL 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define XUSB_PADCTL_IOPHY_USB3_PADX_CTL4(x) (0x068 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_TAP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_TAP_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_AMP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_AMP_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_VAL 0x002008ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(x) ((x) < 2 ? 0x078 + (x) * 4 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0x0f8 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL2_SPARE_IN_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL2_SPARE_IN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL2_SPARE_IN_VAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(x) ((x) < 2 ? 0x090 + (x) * 4 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x11c + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL5_RX_QEYE_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(x) ((x) < 2 ? 0x098 + (x) * 4 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0x128 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_G_Z_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_TAP_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_AMP_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_G_Z 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_TAP 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_AMP 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_CTLE_Z 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_LATCH_G_Z 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x0a0 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(x) ((x) ? 0x0 : 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x0ac + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x0b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x0c0 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWN_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWN_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWP_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEN_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEP_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x0c8 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define XUSB_PADCTL_HSIC_PAD_CTL1_RPU_STROBE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define XUSB_PADCTL_HSIC_PAD_CTL1_RPU_DATA (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define XUSB_PADCTL_HSIC_PAD_CTL1_RPD_STROBE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define XUSB_PADCTL_HSIC_PAD_CTL1_RPD_DATA (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_ZI (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_RX (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_TRX (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_TX (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define XUSB_PADCTL_HSIC_PAD_CTL1_AUTO_TERM_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x0d0 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_STRB_TRIM_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define XUSB_PADCTL_USB3_PAD_MUX 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (6 + (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL0_REFCLK_NDIV_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL0_REFCLK_NDIV_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2 0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL1_CP_CNTL_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL1_CP_CNTL_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL0_CP_CNTL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL0_CP_CNTL_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_TCLKOUT_EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_TXCLKREF_SEL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_XDIGCLK_SEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_XDIGCLK_SEL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL3 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL3_RCAL_BYPASS (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5 0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6 0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct tegra124_xusb_fuse_calibration {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 hs_curr_level[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 hs_iref_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 hs_term_range_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 hs_squelch_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct tegra124_xusb_padctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct tegra_xusb_padctl base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct tegra124_xusb_fuse_calibration fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static inline struct tegra124_xusb_padctl *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) to_tegra124_xusb_padctl(struct tegra_xusb_padctl *padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return container_of(padctl, struct tegra124_xusb_padctl, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int tegra124_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mutex_lock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (padctl->enable++ > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int tegra124_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mutex_lock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (WARN_ON(padctl->enable == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (--padctl->enable > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int tegra124_usb3_save_context(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct tegra_xusb_usb3_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct tegra_xusb_lane *lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 value, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) port = tegra_xusb_find_usb3_port(padctl, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) port->context_saved = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) lane = port->base.lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (lane->pad == padctl->pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) offset = XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) value = padctl_readl(padctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) value &= ~(XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) value |= XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_TAP <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) padctl_writel(padctl, value, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) value = padctl_readl(padctl, offset) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) port->tap1 = value & XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_TAP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) value = padctl_readl(padctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) value &= ~(XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) value |= XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_AMP <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) padctl_writel(padctl, value, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) value = padctl_readl(padctl, offset) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) port->amp = value & XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_AMP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_USB3_PADX_CTL4(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) value &= ~((XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_TAP_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_TAP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_AMP_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_AMP_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) value |= (port->tap1 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_TAP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) (port->amp <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_AMP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_USB3_PADX_CTL4(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) value = padctl_readl(padctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) value &= ~(XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) value |= XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_LATCH_G_Z <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) padctl_writel(padctl, value, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) value = padctl_readl(padctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) value &= ~(XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) value |= XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_G_Z <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) padctl_writel(padctl, value, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) value = padctl_readl(padctl, offset) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) port->ctle_g = value &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_G_Z_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) value = padctl_readl(padctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) value &= ~(XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) value |= XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_CTLE_Z <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) padctl_writel(padctl, value, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) value = padctl_readl(padctl, offset) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) port->ctle_z = value &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_G_Z_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_USB3_PADX_CTL2(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) value &= ~((XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_G_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_G_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) (XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_Z_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_Z_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) value |= (port->ctle_g <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_G_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) (port->ctle_z <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_Z_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_USB3_PADX_CTL2(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int tegra124_hsic_set_idle(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned int index, bool idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) value |= XUSB_PADCTL_HSIC_PAD_CTL1_RPD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) XUSB_PADCTL_HSIC_PAD_CTL1_RPU_STROBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_RPD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) XUSB_PADCTL_HSIC_PAD_CTL1_RPU_STROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define TEGRA124_LANE(_name, _offset, _shift, _mask, _type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .offset = _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .num_funcs = ARRAY_SIZE(tegra124_##_type##_functions), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .funcs = tegra124_##_type##_functions, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const char * const tegra124_usb2_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "snps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) "xusb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct tegra_xusb_lane_soc tegra124_usb2_lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) TEGRA124_LANE("usb2-0", 0x004, 0, 0x3, usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) TEGRA124_LANE("usb2-1", 0x004, 2, 0x3, usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) TEGRA124_LANE("usb2-2", 0x004, 4, 0x3, usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tegra124_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct tegra_xusb_usb2_lane *usb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!usb2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) INIT_LIST_HEAD(&usb2->base.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) usb2->base.soc = &pad->soc->lanes[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) usb2->base.index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) usb2->base.pad = pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) usb2->base.np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) err = tegra_xusb_lane_parse_dt(&usb2->base, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) kfree(usb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return &usb2->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) kfree(usb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct tegra_xusb_lane_ops tegra124_usb2_lane_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .probe = tegra124_usb2_lane_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .remove = tegra124_usb2_lane_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int tegra124_usb2_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return tegra124_xusb_padctl_enable(lane->pad->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int tegra124_usb2_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return tegra124_xusb_padctl_disable(lane->pad->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int tegra124_usb2_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct tegra124_xusb_padctl *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct tegra_xusb_usb2_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned int index = lane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) port = tegra_xusb_find_usb2_port(padctl, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) priv = to_tegra124_xusb_padctl(padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) value |= (priv->fuse.hs_squelch_level <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) value &= ~(XUSB_PADCTL_USB2_PORT_CAP_PORT_CAP_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_SHIFT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) value |= XUSB_PADCTL_USB2_PORT_CAP_HOST <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_SHIFT(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) (XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) (XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) value |= (priv->fuse.hs_curr_level[index] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) usb2->hs_curr_level_offset) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) value |= XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) value |= XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(index) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) (XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) value |= (priv->fuse.hs_term_range_adj <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) (priv->fuse.hs_iref_cap <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) err = regulator_enable(port->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mutex_lock(&pad->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (pad->enable++ > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mutex_unlock(&pad->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int tegra124_usb2_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct tegra_xusb_usb2_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) port = tegra_xusb_find_usb2_port(padctl, lane->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (!port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(&phy->dev, "no port found for USB2 lane %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) lane->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mutex_lock(&pad->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (WARN_ON(pad->enable == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (--pad->enable > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) regulator_disable(port->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) mutex_unlock(&pad->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const struct phy_ops tegra124_usb2_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .init = tegra124_usb2_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .exit = tegra124_usb2_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .power_on = tegra124_usb2_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .power_off = tegra124_usb2_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static struct tegra_xusb_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) tegra124_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) const struct tegra_xusb_pad_soc *soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct tegra_xusb_usb2_pad *usb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct tegra_xusb_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!usb2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mutex_init(&usb2->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pad = &usb2->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pad->ops = &tegra124_usb2_lane_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pad->soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) err = tegra_xusb_pad_init(pad, padctl, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) kfree(usb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) err = tegra_xusb_pad_register(pad, &tegra124_usb2_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dev_set_drvdata(&pad->dev, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) device_unregister(&pad->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static void tegra124_usb2_pad_remove(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) kfree(usb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const struct tegra_xusb_pad_ops tegra124_usb2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .probe = tegra124_usb2_pad_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .remove = tegra124_usb2_pad_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static const struct tegra_xusb_pad_soc tegra124_usb2_pad = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .name = "usb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .num_lanes = ARRAY_SIZE(tegra124_usb2_lanes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .lanes = tegra124_usb2_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .ops = &tegra124_usb2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const char * const tegra124_ulpi_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "snps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "xusb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static const struct tegra_xusb_lane_soc tegra124_ulpi_lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, ulpi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) tegra124_ulpi_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct tegra_xusb_ulpi_lane *ulpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ulpi = kzalloc(sizeof(*ulpi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (!ulpi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) INIT_LIST_HEAD(&ulpi->base.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ulpi->base.soc = &pad->soc->lanes[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ulpi->base.index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ulpi->base.pad = pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ulpi->base.np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) err = tegra_xusb_lane_parse_dt(&ulpi->base, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) kfree(ulpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return &ulpi->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static void tegra124_ulpi_lane_remove(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct tegra_xusb_ulpi_lane *ulpi = to_ulpi_lane(lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) kfree(ulpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const struct tegra_xusb_lane_ops tegra124_ulpi_lane_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .probe = tegra124_ulpi_lane_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .remove = tegra124_ulpi_lane_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int tegra124_ulpi_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return tegra124_xusb_padctl_enable(lane->pad->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int tegra124_ulpi_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return tegra124_xusb_padctl_disable(lane->pad->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static int tegra124_ulpi_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int tegra124_ulpi_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const struct phy_ops tegra124_ulpi_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .init = tegra124_ulpi_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .exit = tegra124_ulpi_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .power_on = tegra124_ulpi_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .power_off = tegra124_ulpi_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static struct tegra_xusb_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) tegra124_ulpi_pad_probe(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) const struct tegra_xusb_pad_soc *soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct tegra_xusb_ulpi_pad *ulpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct tegra_xusb_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ulpi = kzalloc(sizeof(*ulpi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (!ulpi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pad = &ulpi->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) pad->ops = &tegra124_ulpi_lane_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pad->soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) err = tegra_xusb_pad_init(pad, padctl, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) kfree(ulpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) err = tegra_xusb_pad_register(pad, &tegra124_ulpi_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_set_drvdata(&pad->dev, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) device_unregister(&pad->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static void tegra124_ulpi_pad_remove(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct tegra_xusb_ulpi_pad *ulpi = to_ulpi_pad(pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) kfree(ulpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static const struct tegra_xusb_pad_ops tegra124_ulpi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .probe = tegra124_ulpi_pad_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .remove = tegra124_ulpi_pad_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static const struct tegra_xusb_pad_soc tegra124_ulpi_pad = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .name = "ulpi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .num_lanes = ARRAY_SIZE(tegra124_ulpi_lanes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .lanes = tegra124_ulpi_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .ops = &tegra124_ulpi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static const char * const tegra124_hsic_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "snps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "xusb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const struct tegra_xusb_lane_soc tegra124_hsic_lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, hsic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, hsic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) tegra124_hsic_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct tegra_xusb_hsic_lane *hsic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (!hsic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) INIT_LIST_HEAD(&hsic->base.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) hsic->base.soc = &pad->soc->lanes[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) hsic->base.index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) hsic->base.pad = pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) hsic->base.np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) err = tegra_xusb_lane_parse_dt(&hsic->base, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) kfree(hsic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return &hsic->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static void tegra124_hsic_lane_remove(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) kfree(hsic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const struct tegra_xusb_lane_ops tegra124_hsic_lane_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .probe = tegra124_hsic_lane_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .remove = tegra124_hsic_lane_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static int tegra124_hsic_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return tegra124_xusb_padctl_enable(lane->pad->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int tegra124_hsic_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return tegra124_xusb_padctl_disable(lane->pad->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static int tegra124_hsic_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) unsigned int index = lane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) err = regulator_enable(pad->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) padctl_writel(padctl, hsic->strobe_trim,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (hsic->auto_term)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) value |= XUSB_PADCTL_HSIC_PAD_CTL1_AUTO_TERM_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) value &= ~XUSB_PADCTL_HSIC_PAD_CTL1_AUTO_TERM_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) value &= ~((XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEN_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEN_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) (XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEP_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) (XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWN_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWN_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) (XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWP_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWP_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) value |= (hsic->tx_rtune_n <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEN_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) (hsic->tx_rtune_p <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) (hsic->tx_rslew_n <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWN_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) (hsic->tx_rslew_p <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) (XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) value |= (hsic->rx_strobe_trim <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) (hsic->rx_data_trim <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_RPD_STROBE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) XUSB_PADCTL_HSIC_PAD_CTL1_RPU_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) XUSB_PADCTL_HSIC_PAD_CTL1_PD_RX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) XUSB_PADCTL_HSIC_PAD_CTL1_PD_ZI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) XUSB_PADCTL_HSIC_PAD_CTL1_PD_TRX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) XUSB_PADCTL_HSIC_PAD_CTL1_PD_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) value |= XUSB_PADCTL_HSIC_PAD_CTL1_RPD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) XUSB_PADCTL_HSIC_PAD_CTL1_RPU_STROBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int tegra124_hsic_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) unsigned int index = lane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) value |= XUSB_PADCTL_HSIC_PAD_CTL1_PD_RX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) XUSB_PADCTL_HSIC_PAD_CTL1_PD_ZI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) XUSB_PADCTL_HSIC_PAD_CTL1_PD_TRX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) XUSB_PADCTL_HSIC_PAD_CTL1_PD_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) regulator_disable(pad->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static const struct phy_ops tegra124_hsic_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .init = tegra124_hsic_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .exit = tegra124_hsic_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .power_on = tegra124_hsic_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .power_off = tegra124_hsic_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static struct tegra_xusb_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) tegra124_hsic_pad_probe(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) const struct tegra_xusb_pad_soc *soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct tegra_xusb_hsic_pad *hsic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct tegra_xusb_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (!hsic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) pad = &hsic->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pad->ops = &tegra124_hsic_lane_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) pad->soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) err = tegra_xusb_pad_init(pad, padctl, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) kfree(hsic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) err = tegra_xusb_pad_register(pad, &tegra124_hsic_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) dev_set_drvdata(&pad->dev, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) device_unregister(&pad->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static void tegra124_hsic_pad_remove(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct tegra_xusb_hsic_pad *hsic = to_hsic_pad(pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) kfree(hsic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static const struct tegra_xusb_pad_ops tegra124_hsic_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .probe = tegra124_hsic_pad_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .remove = tegra124_hsic_pad_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const struct tegra_xusb_pad_soc tegra124_hsic_pad = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .name = "hsic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .num_lanes = ARRAY_SIZE(tegra124_hsic_lanes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .lanes = tegra124_hsic_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .ops = &tegra124_hsic_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static const char * const tegra124_pcie_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) "pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) "usb3-ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) "sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static const struct tegra_xusb_lane_soc tegra124_pcie_lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) tegra124_pcie_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct tegra_xusb_pcie_lane *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (!pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) INIT_LIST_HEAD(&pcie->base.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) pcie->base.soc = &pad->soc->lanes[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) pcie->base.index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) pcie->base.pad = pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) pcie->base.np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) err = tegra_xusb_lane_parse_dt(&pcie->base, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) kfree(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return &pcie->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static void tegra124_pcie_lane_remove(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) kfree(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const struct tegra_xusb_lane_ops tegra124_pcie_lane_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .probe = tegra124_pcie_lane_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .remove = tegra124_pcie_lane_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int tegra124_pcie_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return tegra124_xusb_padctl_enable(lane->pad->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static int tegra124_pcie_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return tegra124_xusb_padctl_disable(lane->pad->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static int tegra124_pcie_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) timeout = jiffies + msecs_to_jiffies(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static int tegra124_pcie_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static const struct phy_ops tegra124_pcie_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .init = tegra124_pcie_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .exit = tegra124_pcie_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .power_on = tegra124_pcie_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .power_off = tegra124_pcie_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static struct tegra_xusb_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) tegra124_pcie_pad_probe(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) const struct tegra_xusb_pad_soc *soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct tegra_xusb_pcie_pad *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct tegra_xusb_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (!pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) pad = &pcie->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) pad->ops = &tegra124_pcie_lane_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) pad->soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) err = tegra_xusb_pad_init(pad, padctl, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) kfree(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) err = tegra_xusb_pad_register(pad, &tegra124_pcie_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) dev_set_drvdata(&pad->dev, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) device_unregister(&pad->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static void tegra124_pcie_pad_remove(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) kfree(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static const struct tegra_xusb_pad_ops tegra124_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .probe = tegra124_pcie_pad_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .remove = tegra124_pcie_pad_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static const struct tegra_xusb_pad_soc tegra124_pcie_pad = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .name = "pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .num_lanes = ARRAY_SIZE(tegra124_pcie_lanes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .lanes = tegra124_pcie_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .ops = &tegra124_pcie_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static const struct tegra_xusb_lane_soc tegra124_sata_lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) TEGRA124_LANE("sata-0", 0x134, 26, 0x3, pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) tegra124_sata_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct tegra_xusb_sata_lane *sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) sata = kzalloc(sizeof(*sata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (!sata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) INIT_LIST_HEAD(&sata->base.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) sata->base.soc = &pad->soc->lanes[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) sata->base.index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) sata->base.pad = pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) sata->base.np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) err = tegra_xusb_lane_parse_dt(&sata->base, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) kfree(sata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return &sata->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static void tegra124_sata_lane_remove(struct tegra_xusb_lane *lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct tegra_xusb_sata_lane *sata = to_sata_lane(lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) kfree(sata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static const struct tegra_xusb_lane_ops tegra124_sata_lane_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .probe = tegra124_sata_lane_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .remove = tegra124_sata_lane_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int tegra124_sata_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return tegra124_xusb_padctl_enable(lane->pad->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static int tegra124_sata_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return tegra124_xusb_padctl_disable(lane->pad->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static int tegra124_sata_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) int err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) timeout = jiffies + msecs_to_jiffies(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static int tegra124_sata_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct tegra_xusb_padctl *padctl = lane->pad->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static const struct phy_ops tegra124_sata_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .init = tegra124_sata_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .exit = tegra124_sata_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .power_on = tegra124_sata_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .power_off = tegra124_sata_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static struct tegra_xusb_pad *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) tegra124_sata_pad_probe(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) const struct tegra_xusb_pad_soc *soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct tegra_xusb_sata_pad *sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct tegra_xusb_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) sata = kzalloc(sizeof(*sata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (!sata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) pad = &sata->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) pad->ops = &tegra124_sata_lane_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) pad->soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) err = tegra_xusb_pad_init(pad, padctl, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) kfree(sata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) err = tegra_xusb_pad_register(pad, &tegra124_sata_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_set_drvdata(&pad->dev, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) device_unregister(&pad->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static void tegra124_sata_pad_remove(struct tegra_xusb_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct tegra_xusb_sata_pad *sata = to_sata_pad(pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) kfree(sata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static const struct tegra_xusb_pad_ops tegra124_sata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .probe = tegra124_sata_pad_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .remove = tegra124_sata_pad_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static const struct tegra_xusb_pad_soc tegra124_sata_pad = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .name = "sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .num_lanes = ARRAY_SIZE(tegra124_sata_lanes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .lanes = tegra124_sata_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .ops = &tegra124_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static const struct tegra_xusb_pad_soc *tegra124_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) &tegra124_usb2_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) &tegra124_ulpi_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) &tegra124_hsic_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) &tegra124_pcie_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) &tegra124_sata_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static int tegra124_usb2_port_enable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static void tegra124_usb2_port_disable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) tegra124_usb2_port_map(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static const struct tegra_xusb_port_ops tegra124_usb2_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .release = tegra_xusb_usb2_port_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .remove = tegra_xusb_usb2_port_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .enable = tegra124_usb2_port_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .disable = tegra124_usb2_port_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .map = tegra124_usb2_port_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static int tegra124_ulpi_port_enable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static void tegra124_ulpi_port_disable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) tegra124_ulpi_port_map(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return tegra_xusb_find_lane(port->padctl, "ulpi", port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static const struct tegra_xusb_port_ops tegra124_ulpi_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .release = tegra_xusb_ulpi_port_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .enable = tegra124_ulpi_port_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .disable = tegra124_ulpi_port_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .map = tegra124_ulpi_port_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static int tegra124_hsic_port_enable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static void tegra124_hsic_port_disable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) tegra124_hsic_port_map(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return tegra_xusb_find_lane(port->padctl, "hsic", port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static const struct tegra_xusb_port_ops tegra124_hsic_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .release = tegra_xusb_hsic_port_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .enable = tegra124_hsic_port_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .disable = tegra124_hsic_port_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .map = tegra124_hsic_port_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static int tegra124_usb3_port_enable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct tegra_xusb_padctl *padctl = port->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct tegra_xusb_lane *lane = usb3->base.lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) unsigned int index = port->index, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (!usb3->internal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) * and conditionalize based on mux function? This seems to work, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) * might not be the exact proper sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_USB3_PADX_CTL2(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) value &= ~((XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_WANDER_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_WANDER_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) (XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) (XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_CDR_CNTL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_CDR_CNTL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) value |= (XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_WANDER_VAL <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_WANDER_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) (XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_CDR_CNTL_VAL <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_CDR_CNTL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) (XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_VAL <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (usb3->context_saved) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) value &= ~((XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_G_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_G_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) (XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_Z_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_Z_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) value |= (usb3->ctle_g <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_G_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) (usb3->ctle_z <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_Z_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_USB3_PADX_CTL2(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) value = XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (usb3->context_saved) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) value &= ~((XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_TAP_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_TAP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) (XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_AMP_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_AMP_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) value |= (usb3->tap1 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_TAP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) (usb3->amp <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_AMP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_USB3_PADX_CTL4(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (lane->pad == padctl->pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(lane->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) offset = XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) value = padctl_readl(padctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) value &= ~(XUSB_PADCTL_IOPHY_MISC_PAD_CTL2_SPARE_IN_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) XUSB_PADCTL_IOPHY_MISC_PAD_CTL2_SPARE_IN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) value |= XUSB_PADCTL_IOPHY_MISC_PAD_CTL2_SPARE_IN_VAL <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) XUSB_PADCTL_IOPHY_MISC_PAD_CTL2_SPARE_IN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) padctl_writel(padctl, value, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (lane->pad == padctl->pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(lane->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) offset = XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) value = padctl_readl(padctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) value |= XUSB_PADCTL_IOPHY_MISC_PAD_CTL5_RX_QEYE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) padctl_writel(padctl, value, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* Enable SATA PHY when SATA lane is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (lane->pad == padctl->sata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) value &= ~(XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL0_REFCLK_NDIV_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL0_REFCLK_NDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) value |= 0x2 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL0_REFCLK_NDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) value &= ~((XUSB_PADCTL_IOPHY_PLL_S0_CTL2_XDIGCLK_SEL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) XUSB_PADCTL_IOPHY_PLL_S0_CTL2_XDIGCLK_SEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) (XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL1_CP_CNTL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL1_CP_CNTL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) (XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL0_CP_CNTL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL0_CP_CNTL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) XUSB_PADCTL_IOPHY_PLL_S0_CTL2_TCLKOUT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) value |= (0x7 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) XUSB_PADCTL_IOPHY_PLL_S0_CTL2_XDIGCLK_SEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) (0x8 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL1_CP_CNTL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) (0x8 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL0_CP_CNTL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) XUSB_PADCTL_IOPHY_PLL_S0_CTL2_TXCLKREF_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL3_RCAL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) value &= ~XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) value &= ~XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN_EARLY(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) value &= ~XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static void tegra124_usb3_port_disable(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) struct tegra_xusb_padctl *padctl = port->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) value |= XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN_EARLY(port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) value |= XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) usleep_range(250, 350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) value |= XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->index, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static const struct tegra_xusb_lane_map tegra124_usb3_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) { 0, "pcie", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) { 1, "pcie", 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) { 1, "sata", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) { 0, NULL, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static struct tegra_xusb_lane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) tegra124_usb3_port_map(struct tegra_xusb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return tegra_xusb_port_find_lane(port, tegra124_usb3_map, "usb3-ss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) static const struct tegra_xusb_port_ops tegra124_usb3_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .release = tegra_xusb_usb3_port_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .remove = tegra_xusb_usb3_port_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .enable = tegra124_usb3_port_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .disable = tegra124_usb3_port_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .map = tegra124_usb3_port_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) tegra124_xusb_read_fuse_calibration(struct tegra124_xusb_fuse_calibration *fuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) fuse->hs_curr_level[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) fuse->hs_iref_cap =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) (value >> FUSE_SKU_CALIB_HS_IREF_CAP_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) FUSE_SKU_CALIB_HS_IREF_CAP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) fuse->hs_term_range_adj =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) fuse->hs_squelch_level =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) (value >> FUSE_SKU_CALIB_HS_SQUELCH_LEVEL_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) FUSE_SKU_CALIB_HS_SQUELCH_LEVEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static struct tegra_xusb_padctl *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) tegra124_xusb_padctl_probe(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) const struct tegra_xusb_padctl_soc *soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) struct tegra124_xusb_padctl *padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (!padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) padctl->base.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) padctl->base.soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) err = tegra124_xusb_read_fuse_calibration(&padctl->fuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) return &padctl->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static void tegra124_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static const struct tegra_xusb_padctl_ops tegra124_xusb_padctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .probe = tegra124_xusb_padctl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .remove = tegra124_xusb_padctl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .usb3_save_context = tegra124_usb3_save_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .hsic_set_idle = tegra124_hsic_set_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static const char * const tegra124_xusb_padctl_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) "avdd-pll-utmip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) "avdd-pll-erefe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) "avdd-pex-pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) "hvdd-pex-pll-e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) const struct tegra_xusb_padctl_soc tegra124_xusb_padctl_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .num_pads = ARRAY_SIZE(tegra124_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .pads = tegra124_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .ports = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .usb2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .ops = &tegra124_usb2_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .ulpi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .ops = &tegra124_ulpi_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .hsic = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .ops = &tegra124_hsic_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .usb3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .ops = &tegra124_usb3_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .ops = &tegra124_xusb_padctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .supply_names = tegra124_xusb_padctl_supply_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .num_supplies = ARRAY_SIZE(tegra124_xusb_padctl_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) EXPORT_SYMBOL_GPL(tegra124_xusb_padctl_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) MODULE_DESCRIPTION("NVIDIA Tegra 124 XUSB Pad Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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