^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * P2U (PIPE to UPHY) driver for Tegra T194 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Vidya Sagar <vidyas@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define P2U_PERIODIC_EQ_CTRL_GEN4 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define P2U_RX_DEBOUNCE_TIME 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct tegra_p2u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static inline void p2u_writel(struct tegra_p2u *phy, const u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) const u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) writel_relaxed(value, phy->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline u32 p2u_readl(struct tegra_p2u *phy, const u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return readl_relaxed(phy->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int tegra_p2u_power_on(struct phy *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct tegra_p2u *phy = phy_get_drvdata(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) val |= P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) val = p2u_readl(phy, P2U_RX_DEBOUNCE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) val &= ~P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct phy_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .power_on = tegra_p2u_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int tegra_p2u_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct tegra_p2u *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) phy->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (IS_ERR(phy->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return PTR_ERR(phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) platform_set_drvdata(pdev, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) generic_phy = devm_phy_create(dev, NULL, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (IS_ERR(generic_phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return PTR_ERR(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) phy_set_drvdata(generic_phy, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (IS_ERR(phy_provider))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct of_device_id tegra_p2u_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .compatible = "nvidia,tegra194-p2u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MODULE_DEVICE_TABLE(of, tegra_p2u_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct platform_driver tegra_p2u_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .probe = tegra_p2u_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .name = "tegra194-p2u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .of_match_table = tegra_p2u_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) module_platform_driver(tegra_p2u_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MODULE_DESCRIPTION("NVIDIA Tegra194 PIPE2UPHY PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags