Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * STMicroelectronics STM32 USB PHY Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define STM32_USBPHYC_PLL	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define STM32_USBPHYC_MISC	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define STM32_USBPHYC_VERSION	0x3F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* STM32_USBPHYC_PLL bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PLLNDIV			GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PLLFRACIN		GENMASK(25, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PLLEN			BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PLLSTRB			BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PLLSTRBYP		BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PLLFRACCTL		BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PLLDITHEN0		BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PLLDITHEN1		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* STM32_USBPHYC_MISC bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SWITHOST		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* STM32_USBPHYC_VERSION bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MINREV			GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MAJREV			GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static const char * const supplies_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	"vdda1v1",	/* 1V1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	"vdda1v8",	/* 1V8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define NUM_SUPPLIES		ARRAY_SIZE(supplies_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PLL_LOCK_TIME_US	100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PLL_PWR_DOWN_TIME_US	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PLL_FVCO_MHZ		2880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PLL_INFF_MIN_RATE_HZ	19200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PLL_INFF_MAX_RATE_HZ	38400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define HZ_PER_MHZ		1000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) struct pll_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u8 ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u16 frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) struct stm32_usbphyc_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct stm32_usbphyc *usbphyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct regulator_bulk_data supplies[NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	bool active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) struct stm32_usbphyc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct stm32_usbphyc_phy **phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int nphys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	int switch_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	writel_relaxed(readl_relaxed(reg) | bits, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	writel_relaxed(readl_relaxed(reg) & ~bits, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static void stm32_usbphyc_get_pll_params(u32 clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 					 struct pll_params *pll_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned long long fvco, ndiv, frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/*    _
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 *   | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 *   | FVCO = 2880MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 *  <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 *   | NDIV = integer part of input bits to set the LDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 *   |_FRACT = fractional part of input bits to set the LDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 *  =>	PLLNDIV = integer part of (FVCO / (INFF*2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 *  =>	PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ndiv = fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	do_div(ndiv, (clk_rate * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	pll_params->ndiv = (u8)ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	frac = fvco * (1 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	do_div(frac, (clk_rate * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	frac = frac - (ndiv * (1 << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	pll_params->frac = (u16)frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct pll_params pll_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32 clk_rate = clk_get_rate(usbphyc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 ndiv, frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u32 usbphyc_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	    (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (pll_params.frac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		usbphyc_pll |= PLLFRACCTL | frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		FIELD_GET(PLLFRACIN, usbphyc_pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static bool stm32_usbphyc_has_one_phy_active(struct stm32_usbphyc *usbphyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	for (i = 0; i < usbphyc->nphys; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		if (usbphyc->phys[i]->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	bool pllen = (readl_relaxed(pll_reg) & PLLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* Check if one phy port has already configured the pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (pllen && stm32_usbphyc_has_one_phy_active(usbphyc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (pllen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		stm32_usbphyc_clr_bits(pll_reg, PLLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		/* Wait for minimum width of powerdown pulse (ENABLE = Low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		udelay(PLL_PWR_DOWN_TIME_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	ret = stm32_usbphyc_pll_init(usbphyc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	stm32_usbphyc_set_bits(pll_reg, PLLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* Wait for maximum lock time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	udelay(PLL_LOCK_TIME_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (!(readl_relaxed(pll_reg) & PLLEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		dev_err(usbphyc->dev, "PLLEN not set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* Check if other phy port active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (stm32_usbphyc_has_one_phy_active(usbphyc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	stm32_usbphyc_clr_bits(pll_reg, PLLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	/* Wait for minimum width of powerdown pulse (ENABLE = Low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	udelay(PLL_PWR_DOWN_TIME_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (readl_relaxed(pll_reg) & PLLEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		dev_err(usbphyc->dev, "PLL not reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int stm32_usbphyc_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ret = stm32_usbphyc_pll_enable(usbphyc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	usbphyc_phy->active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int stm32_usbphyc_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	usbphyc_phy->active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return stm32_usbphyc_pll_disable(usbphyc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int stm32_usbphyc_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return regulator_bulk_enable(NUM_SUPPLIES, usbphyc_phy->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int stm32_usbphyc_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return regulator_bulk_disable(NUM_SUPPLIES, usbphyc_phy->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct phy_ops stm32_usbphyc_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.init = stm32_usbphyc_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.exit = stm32_usbphyc_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.power_on = stm32_usbphyc_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.power_off = stm32_usbphyc_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 				       u32 utmi_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (!utmi_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				       SWITHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				       SWITHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	usbphyc->switch_setup = utmi_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 					  struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct stm32_usbphyc_phy *usbphyc_phy = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct device_node *phynode = args->np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	int port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	for (port = 0; port < usbphyc->nphys; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			usbphyc_phy = usbphyc->phys[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (!usbphyc_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		dev_err(dev, "failed to find phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	    ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		dev_err(dev, "invalid number of cells for phy port%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			usbphyc_phy->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	/* Configure the UTMI switch for PHY port#2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (usbphyc_phy->index == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		if (usbphyc->switch_setup < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			if (args->args[0] != usbphyc->switch_setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 				dev_err(dev, "phy port1 already used\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 				return ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	return usbphyc_phy->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int stm32_usbphyc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct stm32_usbphyc *usbphyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct device_node *child, *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	int ret, port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (!usbphyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	usbphyc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	dev_set_drvdata(dev, usbphyc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	usbphyc->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (IS_ERR(usbphyc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return PTR_ERR(usbphyc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	usbphyc->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (IS_ERR(usbphyc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		ret = PTR_ERR(usbphyc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		dev_err(dev, "clk get failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ret = clk_prepare_enable(usbphyc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		dev_err(dev, "clk enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	usbphyc->rst = devm_reset_control_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (!IS_ERR(usbphyc->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		reset_control_assert(usbphyc->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		reset_control_deassert(usbphyc->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	usbphyc->switch_setup = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	usbphyc->nphys = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 				     sizeof(*usbphyc->phys), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (!usbphyc->phys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		struct stm32_usbphyc_phy *usbphyc_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			ret = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 				dev_err(dev, "failed to create phy%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 					port, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 					   GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		if (!usbphyc_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		for (i = 0; i < NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			usbphyc_phy->supplies[i].supply = supplies_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		ret = devm_regulator_bulk_get(&phy->dev, NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 					      usbphyc_phy->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 				dev_err(&phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 					"failed to get regulators: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		ret = of_property_read_u32(child, "reg", &index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		if (ret || index > usbphyc->nphys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			dev_err(&phy->dev, "invalid reg property: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 			goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		usbphyc->phys[port] = usbphyc_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		phy_set_bus_width(phy, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		phy_set_drvdata(phy, usbphyc_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		usbphyc->phys[port]->phy = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		usbphyc->phys[port]->usbphyc = usbphyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		usbphyc->phys[port]->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		usbphyc->phys[port]->active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		port++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	phy_provider = devm_of_phy_provider_register(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 						     stm32_usbphyc_of_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		ret = PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		dev_err(dev, "failed to register phy provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	dev_info(dev, "registered rev:%lu.%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	clk_disable_unprepare(usbphyc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int stm32_usbphyc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	clk_disable_unprepare(usbphyc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct of_device_id stm32_usbphyc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	{ .compatible = "st,stm32mp1-usbphyc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static struct platform_driver stm32_usbphyc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	.probe = stm32_usbphyc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.remove = stm32_usbphyc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		.of_match_table = stm32_usbphyc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		.name = "stm32-usbphyc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) module_platform_driver(stm32_usbphyc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MODULE_LICENSE("GPL v2");