Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ST SPEAr1310-miphy driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Pratyush Anand <pratyush.anand@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* SPEAr1310 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SPEAR1310_PCIE_SATA_CFG			0x3A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	#define SPEAR1310_PCIE_SATA2_SEL_PCIE		(0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	#define SPEAR1310_PCIE_SATA1_SEL_PCIE		(0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	#define SPEAR1310_PCIE_SATA0_SEL_PCIE		(0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	#define SPEAR1310_PCIE_SATA2_SEL_SATA		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	#define SPEAR1310_PCIE_SATA1_SEL_SATA		BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	#define SPEAR1310_PCIE_SATA0_SEL_SATA		BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	#define SPEAR1310_SATA2_CFG_TX_CLK_EN		BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	#define SPEAR1310_SATA2_CFG_RX_CLK_EN		BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	#define SPEAR1310_SATA2_CFG_POWERUP_RESET	BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	#define SPEAR1310_SATA2_CFG_PM_CLK_EN		BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	#define SPEAR1310_SATA1_CFG_TX_CLK_EN		BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	#define SPEAR1310_SATA1_CFG_RX_CLK_EN		BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	#define SPEAR1310_SATA1_CFG_POWERUP_RESET	BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	#define SPEAR1310_SATA1_CFG_PM_CLK_EN		BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	#define SPEAR1310_SATA0_CFG_TX_CLK_EN		BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	#define SPEAR1310_SATA0_CFG_RX_CLK_EN		BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	#define SPEAR1310_SATA0_CFG_POWERUP_RESET	BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	#define SPEAR1310_SATA0_CFG_PM_CLK_EN		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	#define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	#define SPEAR1310_PCIE2_CFG_POWERUP_RESET	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	#define SPEAR1310_PCIE2_CFG_CORE_CLK_EN		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	#define SPEAR1310_PCIE2_CFG_AUX_CLK_EN		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	#define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	#define SPEAR1310_PCIE1_CFG_POWERUP_RESET	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	#define SPEAR1310_PCIE1_CFG_CORE_CLK_EN		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	#define SPEAR1310_PCIE1_CFG_AUX_CLK_EN		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	#define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	#define SPEAR1310_PCIE0_CFG_POWERUP_RESET	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	#define SPEAR1310_PCIE0_CFG_CORE_CLK_EN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	#define SPEAR1310_PCIE0_CFG_AUX_CLK_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	#define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	#define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			BIT((x + 29)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	#define SPEAR1310_PCIE_CFG_VAL(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			(SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 			SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	#define SPEAR1310_SATA_CFG_VAL(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			(SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SPEAR1310_PCIE_MIPHY_CFG_1		0x3A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	#define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	#define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2	BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	#define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x)	(x << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	#define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	#define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2	BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	#define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x)	(x << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			(SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define SPEAR1310_PCIE_MIPHY_CFG_2		0x3AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) enum spear1310_miphy_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct spear1310_miphy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/* instance id of this phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32				id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* phy mode: 0 for SATA 1 for PCIe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	enum spear1310_miphy_mode	mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* regmap for any soc specific misc registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct regmap			*misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* phy struct pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct phy			*phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int spear1310_miphy_pcie_init(struct spear1310_miphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			   SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			   SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	switch (priv->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		val = SPEAR1310_PCIE_CFG_VAL(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		val = SPEAR1310_PCIE_CFG_VAL(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		val = SPEAR1310_PCIE_CFG_VAL(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			   SPEAR1310_PCIE_CFG_MASK(priv->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int spear1310_miphy_pcie_exit(struct spear1310_miphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			   SPEAR1310_PCIE_CFG_MASK(priv->id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			   SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int spear1310_miphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (priv->mode == PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		ret = spear1310_miphy_pcie_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int spear1310_miphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (priv->mode == PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		ret = spear1310_miphy_pcie_exit(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct of_device_id spear1310_miphy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	{ .compatible = "st,spear1310-miphy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MODULE_DEVICE_TABLE(of, spear1310_miphy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct phy_ops spear1310_miphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.init = spear1310_miphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.exit = spear1310_miphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct phy *spear1310_miphy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 					 struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct spear1310_miphy_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (args->args_count < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		dev_err(dev, "DT did not pass correct no of args\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	priv->mode = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (priv->mode != SATA && priv->mode != PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		dev_err(dev, "DT did not pass correct phy mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return priv->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int spear1310_miphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct spear1310_miphy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	priv->misc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (IS_ERR(priv->misc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		dev_err(dev, "failed to find misc regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return PTR_ERR(priv->misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (of_property_read_u32(dev->of_node, "phy-id", &priv->id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		dev_err(dev, "failed to find phy id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	priv->phy = devm_phy_create(dev, NULL, &spear1310_miphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (IS_ERR(priv->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		dev_err(dev, "failed to create SATA PCIe PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return PTR_ERR(priv->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	phy_set_drvdata(priv->phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	phy_provider =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		devm_of_phy_provider_register(dev, spear1310_miphy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		dev_err(dev, "failed to register phy provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct platform_driver spear1310_miphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.probe		= spear1310_miphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.name = "spear1310-miphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.of_match_table = of_match_ptr(spear1310_miphy_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) module_platform_driver(spear1310_miphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_DESCRIPTION("ST SPEAR1310-MIPHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MODULE_AUTHOR("Pratyush Anand <pratyush.anand@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MODULE_LICENSE("GPL v2");