^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Alexandre Torgue <alexandre.torgue@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* MiPHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MIPHY_CONF_RESET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RST_APPLI_SW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RST_CONF_SW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RST_MACRO_SW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MIPHY_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RST_PLL_SW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RST_COMP_SW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MIPHY_STATUS_1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PHY_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HFC_RDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HFC_PLL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MIPHY_CONTROL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TERM_EN_SW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DIS_LINK_RST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AUTO_RST_RX BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PX_RX_POL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MIPHY_BOUNDARY_SEL 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TX_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SSC_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GENSEL_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MIPHY_BOUNDARY_1 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MIPHY_BOUNDARY_2 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SSC_EN_SW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MIPHY_PLL_CLKREF_FREQ 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MIPHY_SPEED 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TX_SPDSEL_80DEC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TX_SPDSEL_40DEC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TX_SPDSEL_20DEC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RX_SPDSEL_80DEC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RX_SPDSEL_40DEC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RX_SPDSEL_20DEC (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MIPHY_CONF 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MIPHY_CTRL_TEST_SEL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MIPHY_CTRL_TEST_1 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MIPHY_CTRL_TEST_2 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MIPHY_CTRL_TEST_3 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MIPHY_CTRL_TEST_4 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MIPHY_FEEDBACK_TEST 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MIPHY_DEBUG_BUS 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MIPHY_DEBUG_STATUS_MSB 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MIPHY_DEBUG_STATUS_LSB 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MIPHY_PWR_RAIL_1 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MIPHY_PWR_RAIL_2 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MIPHY_SYNCHAR_CONTROL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MIPHY_COMP_FSM_1 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define COMP_START BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MIPHY_COMP_FSM_6 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define COMP_DONE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MIPHY_COMP_POSTP 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MIPHY_TX_CTRL_1 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TX_REG_STEP_0V 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TX_REG_STEP_P_25MV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TX_REG_STEP_P_50MV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TX_REG_STEP_N_25MV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TX_REG_STEP_N_50MV 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TX_REG_STEP_N_75MV 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MIPHY_TX_CTRL_2 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TX_SLEW_SW_40_PS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TX_SLEW_SW_80_PS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TX_SLEW_SW_120_PS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MIPHY_TX_CTRL_3 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MIPHY_TX_CAL_MAN 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TX_SLEW_CAL_MAN_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MIPHY_TST_BIAS_BOOST_2 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MIPHY_BIAS_BOOST_1 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MIPHY_BIAS_BOOST_2 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MIPHY_RX_DESBUFF_FDB_2 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MIPHY_RX_DESBUFF_FDB_3 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MIPHY_SIGDET_COMPENS1 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MIPHY_SIGDET_COMPENS2 0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MIPHY_JITTER_PERIOD 0x6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MIPHY_JITTER_AMPLITUDE_1 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MIPHY_JITTER_AMPLITUDE_2 0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MIPHY_JITTER_AMPLITUDE_3 0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MIPHY_RX_K_GAIN 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MIPHY_RX_BUFFER_CTRL 0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VGA_GAIN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EQ_DC_GAIN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EQ_BOOST_GAIN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MIPHY_RX_VGA_GAIN 0x7b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MIPHY_RX_EQU_GAIN_1 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MIPHY_RX_EQU_GAIN_2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MIPHY_RX_EQU_GAIN_3 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MIPHY_RX_CAL_CTRL_1 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MIPHY_RX_CAL_CTRL_2 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MIPHY_RX_CAL_OFFSET_CTRL 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CAL_OFFSET_VGA_64 (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CAL_OFFSET_THRESHOLD_64 (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VGA_OFFSET_POLARITY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OFFSET_COMPENSATION_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MIPHY_RX_CAL_VGA_STEP 0x9a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MIPHY_RX_CAL_EYE_MIN 0x9d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MIPHY_RX_CAL_OPT_LENGTH 0x9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MIPHY_RX_LOCK_CTRL_1 0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MIPHY_RX_LOCK_SETTINGS_OPT 0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MIPHY_RX_LOCK_STEP 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MIPHY_RX_SIGDET_SLEEP_OA 0xc9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MIPHY_RX_SIGDET_SLEEP_SEL 0xca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MIPHY_RX_SIGDET_WAIT_SEL 0xcb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MIPHY_RX_SIGDET_DATA_SEL 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define EN_ULTRA_LOW_POWER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EN_FIRST_HALF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EN_SECOND_HALF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EN_DIGIT_SIGNAL_CHECK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MIPHY_RX_POWER_CTRL_1 0xcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MIPHY_RX_POWER_CTRL_2 0xce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MIPHY_PLL_CALSET_CTRL 0xd3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MIPHY_PLL_CALSET_1 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MIPHY_PLL_CALSET_2 0xd5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MIPHY_PLL_CALSET_3 0xd6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MIPHY_PLL_CALSET_4 0xd7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MIPHY_PLL_SBR_1 0xe3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SET_NEW_CHANGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MIPHY_PLL_SBR_2 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MIPHY_PLL_SBR_3 0xe5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MIPHY_PLL_SBR_4 0xe6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MIPHY_PLL_COMMON_MISC_2 0xe9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define START_ACT_FILT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MIPHY_PLL_SPAREIN 0xeb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * On STiH407 the glue logic can be different among MiPHY devices; for example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * MiPHY0: OSC_FORCE_EXT means:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * MiPHY1: OSC_FORCE_EXT means:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Some devices have not the possibility to check if the osc is ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MIPHY_OSC_FORCE_EXT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MIPHY_OSC_RDY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MIPHY_CTRL_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MIPHY_CTRL_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MIPHY_CTRL_SYNC_D_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* SATA / PCIe defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SATA_CTRL_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PCIE_CTRL_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SATA_CTRL_SELECT_SATA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SATA_CTRL_SELECT_PCIE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SYSCFG_PCIE_PCIE_VAL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SATA_SPDMODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MIPHY_SATA_BANK_NB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MIPHY_PCIE_BANK_NB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SYSCFG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SYSCFG_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SYSCFG_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) SYSCFG_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SYSCFG_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct miphy28lp_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct miphy28lp_dev *phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void __iomem *pipebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) bool osc_force_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bool osc_rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bool px_rx_pol_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bool ssc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) bool tx_impedance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct reset_control *miphy_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 sata_gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Sysconfig registers offsets needed to configure the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 syscfg_reg[SYSCFG_REG_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct miphy28lp_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct mutex miphy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct miphy28lp_phy **phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int nphys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct miphy_initval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct pll_ratio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int clk_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int calset_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int calset_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int calset_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int calset_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int cal_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct pll_ratio sata_pll_ratio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .clk_ref = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .calset_1 = 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .calset_2 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .calset_3 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .calset_4 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .cal_ctrl = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct pll_ratio pcie_pll_ratio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .clk_ref = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .calset_1 = 0xa6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .calset_2 = 0xaa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .calset_3 = 0xaa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .calset_4 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .cal_ctrl = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct pll_ratio usb3_pll_ratio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .clk_ref = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .calset_1 = 0xa6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .calset_2 = 0xaa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .calset_3 = 0xaa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .calset_4 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .cal_ctrl = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct miphy28lp_pll_gen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int bias_boost_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int bias_boost_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int tx_ctrl_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int tx_ctrl_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int tx_ctrl_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int rx_k_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int rx_vga_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int rx_equ_gain_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int rx_equ_gain_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int rx_equ_gain_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int rx_buff_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct miphy28lp_pll_gen sata_pll_gen[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .bank = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .speed = TX_SPDSEL_80DEC | RX_SPDSEL_80DEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .bias_boost_1 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .bias_boost_2 = 0xae,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .tx_ctrl_2 = 0x53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .tx_ctrl_3 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .rx_vga_gain = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .rx_equ_gain_1 = 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .rx_equ_gain_2 = 0x56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .rx_equ_gain_3 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .bank = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .bias_boost_1 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .bias_boost_2 = 0xae,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .tx_ctrl_2 = 0x72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .tx_ctrl_3 = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .rx_vga_gain = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .rx_equ_gain_1 = 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .rx_equ_gain_2 = 0x56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .rx_equ_gain_3 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .bank = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .bias_boost_1 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .bias_boost_2 = 0xae,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .tx_ctrl_2 = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .tx_ctrl_3 = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .rx_vga_gain = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .rx_equ_gain_1 = 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .rx_equ_gain_2 = 0x56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .rx_equ_gain_3 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static struct miphy28lp_pll_gen pcie_pll_gen[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .bank = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .bias_boost_1 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .bias_boost_2 = 0xa5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .tx_ctrl_1 = TX_REG_STEP_N_25MV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .tx_ctrl_2 = 0x71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .tx_ctrl_3 = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .rx_k_gain = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .rx_vga_gain = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .rx_equ_gain_1 = 0x79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .rx_equ_gain_2 = 0x56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .bank = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .bias_boost_1 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .bias_boost_2 = 0xa5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .tx_ctrl_1 = TX_REG_STEP_N_25MV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .tx_ctrl_2 = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .tx_ctrl_3 = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .rx_k_gain = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .rx_vga_gain = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .rx_equ_gain_1 = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .rx_equ_gain_2 = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static inline void miphy28lp_set_reset(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) void __iomem *base = miphy_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Putting Macro in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val = RST_APPLI_SW | RST_CONF_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) writeb_relaxed(val, base + MIPHY_CONF_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Bringing the MIPHY-CPU registers out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (miphy_phy->type == PHY_TYPE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) val = AUTO_RST_RX | TERM_EN_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) writeb_relaxed(val, base + MIPHY_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) val = AUTO_RST_RX | TERM_EN_SW | DIS_LINK_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writeb_relaxed(val, base + MIPHY_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static inline void miphy28lp_pll_calibration(struct miphy28lp_phy *miphy_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct pll_ratio *pll_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) void __iomem *base = miphy_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Applying PLL Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* PLL Ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) val = (0x68 << 1) | TX_SLEW_CAL_MAN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) writeb_relaxed(val, base + MIPHY_TX_CAL_MAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val = VGA_OFFSET_POLARITY | CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (miphy_phy->type != PHY_TYPE_SATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) val |= OFFSET_COMPENSATION_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (miphy_phy->type == PHY_TYPE_USB3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) writeb_relaxed(0x00, base + MIPHY_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) val = EN_DIGIT_SIGNAL_CHECK | EN_FIRST_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static inline void miphy28lp_sata_config_gen(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) void __iomem *base = miphy_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) for (i = 0; i < ARRAY_SIZE(sata_pll_gen); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct miphy28lp_pll_gen *gen = &sata_pll_gen[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Banked settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) writeb_relaxed(gen->bank, base + MIPHY_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) writeb_relaxed(gen->speed, base + MIPHY_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* TX buffer Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* RX Buffer Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static inline void miphy28lp_pcie_config_gen(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) void __iomem *base = miphy_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) for (i = 0; i < ARRAY_SIZE(pcie_pll_gen); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct miphy28lp_pll_gen *gen = &pcie_pll_gen[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Banked settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) writeb_relaxed(gen->bank, base + MIPHY_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) writeb_relaxed(gen->speed, base + MIPHY_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* TX buffer Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* RX Buffer Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned long finish = jiffies + 5 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Waiting for Compensation to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (time_after_eq(jiffies, finish))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } while (!(val & COMP_DONE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static inline int miphy28lp_compensation(struct miphy28lp_phy *miphy_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct pll_ratio *pll_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) void __iomem *base = miphy_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Poll for HFC ready after reset release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Compensation measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (miphy_phy->type == PHY_TYPE_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) writeb_relaxed(0x00, base + MIPHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* TX compensation offset to re-center TX impedance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) writeb_relaxed(0x00, base + MIPHY_COMP_POSTP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (miphy_phy->type == PHY_TYPE_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return miphy28lp_wait_compensation(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static inline void miphy28_usb3_miphy_reset(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) void __iomem *base = miphy_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* MIPHY Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) val = RST_COMP_SW | RST_PLL_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) writeb_relaxed(val, base + MIPHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) writeb_relaxed(0x00, base + MIPHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) writeb_relaxed(0x00, base + MIPHY_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) writeb_relaxed(0x00, base + MIPHY_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) writeb_relaxed(0x00, base + MIPHY_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) void __iomem *base = miphy_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Compensate Tx impedance to avoid out of range values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * Enable the SSC on PLL for all banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) val = readb_relaxed(base + MIPHY_BOUNDARY_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) val |= SSC_EN_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) val |= SSC_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) for (val = 0; val < MIPHY_SATA_BANK_NB; val++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) writeb_relaxed(val, base + MIPHY_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Add value to each reference clock cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* and define the period length of the SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Clear any previous request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* requests the PLL to take in account new parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* To be sure there is no other pending requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) void __iomem *base = miphy_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Compensate Tx impedance to avoid out of range values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * Enable the SSC on PLL for all banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) val = readb_relaxed(base + MIPHY_BOUNDARY_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) val |= SSC_EN_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) val |= SSC_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) for (val = 0; val < MIPHY_PCIE_BANK_NB; val++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) writeb_relaxed(val, base + MIPHY_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Validate Step component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Validate Period component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Clear any previous request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* requests the PLL to take in account new parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* To be sure there is no other pending requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static inline void miphy_tune_tx_impedance(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Compensate Tx impedance to avoid out of range values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) void __iomem *base = miphy_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Putting Macro in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) miphy28lp_set_reset(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* PLL calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) miphy28lp_pll_calibration(miphy_phy, &sata_pll_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Banked settings Gen1/Gen2/Gen3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) miphy28lp_sata_config_gen(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Power control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Input bridge enable, manual input bridge control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* Macro out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Poll for HFC ready after reset release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Compensation measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) err = miphy28lp_compensation(miphy_phy, &sata_pll_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (miphy_phy->px_rx_pol_inv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Invert Rx polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) val |= PX_RX_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (miphy_phy->ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) miphy_sata_tune_ssc(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (miphy_phy->tx_impedance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) miphy_tune_tx_impedance(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static inline int miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) void __iomem *base = miphy_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Putting Macro in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) miphy28lp_set_reset(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* PLL calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) miphy28lp_pll_calibration(miphy_phy, &pcie_pll_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Banked settings Gen1/Gen2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) miphy28lp_pcie_config_gen(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* Power control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Input bridge enable, manual input bridge control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Macro out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Poll for HFC ready after reset release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Compensation measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) err = miphy28lp_compensation(miphy_phy, &pcie_pll_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (miphy_phy->ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) miphy_pcie_tune_ssc(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (miphy_phy->tx_impedance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) miphy_tune_tx_impedance(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) void __iomem *base = miphy_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* Putting Macro in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) miphy28lp_set_reset(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* PLL calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) miphy28lp_pll_calibration(miphy_phy, &usb3_pll_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Writing The Speed Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) writeb_relaxed(0x00, base + MIPHY_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) val = RX_SPDSEL_20DEC | TX_SPDSEL_20DEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) writeb_relaxed(val, base + MIPHY_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* RX Channel compensation and calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) val = OFFSET_COMPENSATION_EN | VGA_OFFSET_POLARITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) val = EQ_DC_GAIN | VGA_GAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* TX compensation offset to re-center TX impedance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) writeb_relaxed(0x02, base + MIPHY_COMP_POSTP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Enable GENSEL_SEL and SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* TX_SEL=0 swing preemp forced by pipe registres */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) val = SSC_SEL | GENSEL_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* MIPHY Bias boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* SSC modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* MIPHY TX control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) writeb_relaxed(0x00, base + MIPHY_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Validate Step component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* Validate Period component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Clear any previous request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* requests the PLL to take in account new parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* To be sure there is no other pending requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Rx PI controller settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* MIPHY RX input bridge control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* INPUT_BRIDGE_EN_SW=1, manual input bridge control[0]=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* MIPHY Reset for usb3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) miphy28_usb3_miphy_reset(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) unsigned long finish = jiffies + 5 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u8 mask = HFC_PLL | HFC_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * For PCIe and USB3 check only that PLL and HFC are ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * For SATA check also that phy is ready!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (miphy_phy->type == PHY_TYPE_SATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) mask |= PHY_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if ((val & mask) != mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) } while (!time_after_eq(jiffies, finish));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) unsigned long finish = jiffies + 5 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (!miphy_phy->osc_rdy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (!miphy_phy->syscfg_reg[SYSCFG_STATUS])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) regmap_read(miphy_dev->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) miphy_phy->syscfg_reg[SYSCFG_STATUS], &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) } while (!time_after_eq(jiffies, finish));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int miphy28lp_get_resource_byname(struct device_node *child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) char *rname, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) index = of_property_match_string(child, "reg-names", rname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return of_address_to_resource(child, index, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int miphy28lp_get_one_addr(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct device_node *child, char *rname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) void __iomem **base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret = miphy28lp_get_resource_byname(child, rname, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) *base = devm_ioremap(dev, res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (!*base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_err(dev, "failed to ioremap %s address region\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) , rname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* MiPHY reset and sysconf setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (!miphy_phy->syscfg_reg[SYSCFG_CTRL])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) err = reset_control_assert(miphy_phy->miphy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (miphy_phy->osc_force_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) miphy_val |= MIPHY_OSC_FORCE_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) regmap_update_bits(miphy_dev->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) miphy_phy->syscfg_reg[SYSCFG_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) MIPHY_CTRL_MASK, miphy_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) err = reset_control_deassert(miphy_phy->miphy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return miphy_osc_is_ready(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int err, sata_conf = SATA_CTRL_SELECT_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) (!miphy_phy->syscfg_reg[SYSCFG_PCI]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) (!miphy_phy->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Configure the glue-logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) regmap_update_bits(miphy_dev->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) miphy_phy->syscfg_reg[SYSCFG_SATA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) SATA_CTRL_MASK, sata_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PCIE_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* MiPHY path and clocking init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dev_err(miphy_dev->dev, "SATA phy setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* initialize miphy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) miphy28lp_configure_sata(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return miphy_is_ready(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) (!miphy_phy->syscfg_reg[SYSCFG_PCI])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) || (!miphy_phy->base) || (!miphy_phy->pipebase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* Configure the glue-logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) regmap_update_bits(miphy_dev->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) miphy_phy->syscfg_reg[SYSCFG_SATA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) SATA_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) PCIE_CTRL_MASK, SYSCFG_PCIE_PCIE_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* MiPHY path and clocking init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) dev_err(miphy_dev->dev, "PCIe phy setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* initialize miphy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) err = miphy28lp_configure_pcie(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* PIPE Wrapper Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* Wait for phy_ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return miphy_is_ready(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static int miphy28lp_init_usb3(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if ((!miphy_phy->base) || (!miphy_phy->pipebase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* MiPHY path and clocking init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_SYNC_D_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev_err(miphy_dev->dev, "USB3 phy setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* initialize miphy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) miphy28lp_configure_usb3(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* PIPE Wrapper Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return miphy_is_ready(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static int miphy28lp_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct miphy28lp_phy *miphy_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) mutex_lock(&miphy_dev->miphy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) switch (miphy_phy->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) case PHY_TYPE_SATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = miphy28lp_init_sata(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) case PHY_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = miphy28lp_init_pcie(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) case PHY_TYPE_USB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ret = miphy28lp_init_usb3(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) mutex_unlock(&miphy_dev->miphy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int miphy28lp_get_addr(struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct device_node *phynode = miphy_phy->phy->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if ((miphy_phy->type != PHY_TYPE_SATA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) (miphy_phy->type != PHY_TYPE_PCIE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) (miphy_phy->type != PHY_TYPE_USB3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) err = miphy28lp_get_one_addr(miphy_dev->dev, phynode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) &miphy_phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if ((miphy_phy->type == PHY_TYPE_PCIE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) (miphy_phy->type == PHY_TYPE_USB3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) &miphy_phy->pipebase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static struct phy *miphy28lp_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct miphy28lp_dev *miphy_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct miphy28lp_phy *miphy_phy = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct device_node *phynode = args->np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) int ret, index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (args->args_count != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dev_err(dev, "Invalid number of cells in 'phy' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) for (index = 0; index < miphy_dev->nphys; index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) miphy_phy = miphy_dev->phys[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (!miphy_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dev_err(dev, "Failed to find appropriate phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) miphy_phy->type = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ret = miphy28lp_get_addr(miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return miphy_phy->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static const struct phy_ops miphy28lp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .init = miphy28lp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static int miphy28lp_probe_resets(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) miphy_phy->miphy_rst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) of_reset_control_get_shared(node, "miphy-sw-rst");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (IS_ERR(miphy_phy->miphy_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dev_err(miphy_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) "miphy soft reset control not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return PTR_ERR(miphy_phy->miphy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) err = reset_control_deassert(miphy_phy->miphy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static int miphy28lp_of_probe(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct miphy28lp_phy *miphy_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) u32 ctrlreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) miphy_phy->osc_force_ext =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) of_property_read_bool(np, "st,osc-force-ext");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) miphy_phy->px_rx_pol_inv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) of_property_read_bool(np, "st,px_rx_pol_inv");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) miphy_phy->tx_impedance =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) of_property_read_bool(np, "st,tx-impedance-comp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (!miphy_phy->sata_gen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) miphy_phy->sata_gen = SATA_GEN1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) for (i = 0; i < SYSCFG_REG_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (!of_property_read_u32_index(np, "st,syscfg", i, &ctrlreg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) miphy_phy->syscfg_reg[i] = ctrlreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static int miphy28lp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct device_node *child, *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct miphy28lp_dev *miphy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) int ret, port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (!miphy_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) miphy_dev->nphys = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) sizeof(*miphy_dev->phys), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (!miphy_dev->phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (IS_ERR(miphy_dev->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) dev_err(miphy_dev->dev, "No syscfg phandle specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return PTR_ERR(miphy_dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) miphy_dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dev_set_drvdata(&pdev->dev, miphy_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) mutex_init(&miphy_dev->miphy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct miphy28lp_phy *miphy_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (!miphy_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) miphy_dev->phys[port] = miphy_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) dev_err(&pdev->dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) ret = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) miphy_dev->phys[port]->phy = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) miphy_dev->phys[port]->phydev = miphy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ret = miphy28lp_of_probe(child, miphy_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) phy_set_drvdata(phy, miphy_dev->phys[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) port++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return PTR_ERR_OR_ZERO(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static const struct of_device_id miphy28lp_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {.compatible = "st,miphy28lp-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) MODULE_DEVICE_TABLE(of, miphy28lp_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static struct platform_driver miphy28lp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .probe = miphy28lp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .name = "miphy28lp-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .of_match_table = miphy28lp_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) module_platform_driver(miphy28lp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) MODULE_DESCRIPTION("STMicroelectronics miphy28lp driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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