^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * phy-uniphier-usb3ss.c - SS-PHY driver for Socionext UniPhier USB3 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2015-2018 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contributors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Motoya Tanigawa <tanigawa.motoya@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Masami Hiramatsu <masami.hiramatsu@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SSPHY_TESTI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TESTI_DAT_MASK GENMASK(13, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TESTI_ADR_MASK GENMASK(5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TESTI_WR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SSPHY_TESTO 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TESTO_DAT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PHY_F(regno, msb, lsb) { (regno), (msb), (lsb) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CDR_CPD_TRIM PHY_F(7, 3, 0) /* RxPLL charge pump current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CDR_CPF_TRIM PHY_F(8, 3, 0) /* RxPLL charge pump current 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TX_PLL_TRIM PHY_F(9, 3, 0) /* TxPLL charge pump current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BGAP_TRIM PHY_F(11, 3, 0) /* Bandgap voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CDR_TRIM PHY_F(13, 6, 5) /* Clock Data Recovery setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VCO_CTRL PHY_F(26, 7, 4) /* VCO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VCOPLL_CTRL PHY_F(27, 2, 0) /* TxPLL VCO tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VCOPLL_CM PHY_F(28, 1, 0) /* TxPLL voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAX_PHY_PARAMS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct uniphier_u3ssphy_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int reg_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct uniphier_u3ssphy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct clk *clk, *clk_ext, *clk_parent, *clk_parent_gio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct reset_control *rst, *rst_parent, *rst_parent_gio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct regulator *vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const struct uniphier_u3ssphy_soc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct uniphier_u3ssphy_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) bool is_legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int nparams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const struct uniphier_u3ssphy_param param[MAX_PHY_PARAMS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void uniphier_u3ssphy_testio_write(struct uniphier_u3ssphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* need to read TESTO twice after accessing TESTI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writel(data, priv->base + SSPHY_TESTI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) readl(priv->base + SSPHY_TESTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) readl(priv->base + SSPHY_TESTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void uniphier_u3ssphy_set_param(struct uniphier_u3ssphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const struct uniphier_u3ssphy_param *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 field_mask = GENMASK(p->field.msb, p->field.lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* read previous data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) val = FIELD_PREP(TESTI_DAT_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) uniphier_u3ssphy_testio_write(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val = readl(priv->base + SSPHY_TESTO) & TESTO_DAT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* update value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val &= ~field_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) data = field_mask & (p->value << p->field.lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val = FIELD_PREP(TESTI_DAT_MASK, data | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) uniphier_u3ssphy_testio_write(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) uniphier_u3ssphy_testio_write(priv, val | TESTI_WR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) uniphier_u3ssphy_testio_write(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* read current data as dummy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val = FIELD_PREP(TESTI_DAT_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) uniphier_u3ssphy_testio_write(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) readl(priv->base + SSPHY_TESTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int uniphier_u3ssphy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = clk_prepare_enable(priv->clk_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) goto out_clk_ext_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = reset_control_deassert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (priv->vbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = regulator_enable(priv->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) goto out_rst_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) out_rst_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reset_control_assert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) out_clk_ext_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) clk_disable_unprepare(priv->clk_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int uniphier_u3ssphy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (priv->vbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) regulator_disable(priv->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reset_control_assert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clk_disable_unprepare(priv->clk_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int uniphier_u3ssphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = clk_prepare_enable(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = clk_prepare_enable(priv->clk_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = reset_control_deassert(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto out_clk_gio_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = reset_control_deassert(priv->rst_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto out_rst_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (priv->data->is_legacy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for (i = 0; i < priv->data->nparams; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) uniphier_u3ssphy_set_param(priv, &priv->data->param[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) out_rst_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) reset_control_assert(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) out_clk_gio_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) clk_disable_unprepare(priv->clk_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) clk_disable_unprepare(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int uniphier_u3ssphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) reset_control_assert(priv->rst_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reset_control_assert(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clk_disable_unprepare(priv->clk_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clk_disable_unprepare(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct phy_ops uniphier_u3ssphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .init = uniphier_u3ssphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .exit = uniphier_u3ssphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .power_on = uniphier_u3ssphy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .power_off = uniphier_u3ssphy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int uniphier_u3ssphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct uniphier_u3ssphy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) priv->data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (WARN_ON(!priv->data ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) priv->data->nparams > MAX_PHY_PARAMS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!priv->data->is_legacy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) priv->clk = devm_clk_get(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) priv->clk_ext = devm_clk_get_optional(dev, "phy-ext");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (IS_ERR(priv->clk_ext))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return PTR_ERR(priv->clk_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) priv->rst = devm_reset_control_get_shared(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (IS_ERR(priv->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return PTR_ERR(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) priv->clk_parent_gio = devm_clk_get(dev, "gio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (IS_ERR(priv->clk_parent_gio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return PTR_ERR(priv->clk_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) priv->rst_parent_gio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) devm_reset_control_get_shared(dev, "gio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (IS_ERR(priv->rst_parent_gio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return PTR_ERR(priv->rst_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) priv->clk_parent = devm_clk_get(dev, "link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (IS_ERR(priv->clk_parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return PTR_ERR(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) priv->rst_parent = devm_reset_control_get_shared(dev, "link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (IS_ERR(priv->rst_parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return PTR_ERR(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) priv->vbus = devm_regulator_get_optional(dev, "vbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (IS_ERR(priv->vbus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return PTR_ERR(priv->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) priv->vbus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) phy = devm_phy_create(dev, dev->of_node, &uniphier_u3ssphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (IS_ERR(phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) phy_set_drvdata(phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct uniphier_u3ssphy_soc_data uniphier_pro4_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .is_legacy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct uniphier_u3ssphy_soc_data uniphier_pxs2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .is_legacy = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .nparams = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { CDR_CPD_TRIM, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { CDR_CPF_TRIM, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { TX_PLL_TRIM, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { BGAP_TRIM, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { CDR_TRIM, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { VCOPLL_CTRL, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { VCOPLL_CM, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct uniphier_u3ssphy_soc_data uniphier_ld20_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .is_legacy = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .nparams = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { CDR_CPD_TRIM, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { CDR_TRIM, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { VCO_CTRL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct of_device_id uniphier_u3ssphy_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .compatible = "socionext,uniphier-pro4-usb3-ssphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .data = &uniphier_pro4_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .compatible = "socionext,uniphier-pro5-usb3-ssphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .data = &uniphier_pro4_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .compatible = "socionext,uniphier-pxs2-usb3-ssphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .data = &uniphier_pxs2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .compatible = "socionext,uniphier-ld20-usb3-ssphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .data = &uniphier_ld20_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .compatible = "socionext,uniphier-pxs3-usb3-ssphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .data = &uniphier_ld20_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MODULE_DEVICE_TABLE(of, uniphier_u3ssphy_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct platform_driver uniphier_u3ssphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .probe = uniphier_u3ssphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .name = "uniphier-usb3-ssphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .of_match_table = uniphier_u3ssphy_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) module_platform_driver(uniphier_u3ssphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MODULE_DESCRIPTION("UniPhier SS-PHY driver for USB3 controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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