^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * phy-uniphier-usb3hs.c - HS-PHY driver for Socionext UniPhier USB3 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2015-2018 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contributors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Motoya Tanigawa <tanigawa.motoya@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Masami Hiramatsu <masami.hiramatsu@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HSPHY_CFG0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HSPHY_CFG0_HS_I_MASK GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HSPHY_CFG0_HSDISC_MASK GENMASK(27, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HSPHY_CFG0_SWING_MASK GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HSPHY_CFG0_SEL_T_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HSPHY_CFG0_RTERM_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HSPHY_CFG0_TRIMMASK (HSPHY_CFG0_HS_I_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) | HSPHY_CFG0_SEL_T_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) | HSPHY_CFG0_RTERM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HSPHY_CFG1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HSPHY_CFG1_DAT_EN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HSPHY_CFG1_ADR_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HSPHY_CFG1_ADR_MASK GENMASK(27, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HSPHY_CFG1_DAT_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PHY_F(regno, msb, lsb) { (regno), (msb), (lsb) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RX_CHK_SYNC PHY_F(0, 5, 5) /* RX sync mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RX_SYNC_SEL PHY_F(1, 1, 0) /* RX sync length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LS_SLEW PHY_F(10, 6, 6) /* LS mode slew rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FS_LS_DRV PHY_F(10, 5, 5) /* FS/LS slew rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX_PHY_PARAMS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct uniphier_u3hsphy_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int reg_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct uniphier_u3hsphy_trim_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int rterm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int sel_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int hs_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define trim_param_is_valid(p) ((p)->rterm || (p)->sel_t || (p)->hs_i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct uniphier_u3hsphy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk *clk, *clk_parent, *clk_ext, *clk_parent_gio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct reset_control *rst, *rst_parent, *rst_parent_gio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct regulator *vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const struct uniphier_u3hsphy_soc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct uniphier_u3hsphy_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bool is_legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int nparams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const struct uniphier_u3hsphy_param param[MAX_PHY_PARAMS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 config0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void (*trim_func)(struct uniphier_u3hsphy_priv *priv, u32 *pconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct uniphier_u3hsphy_trim_param *pt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void uniphier_u3hsphy_trim_ld20(struct uniphier_u3hsphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 *pconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct uniphier_u3hsphy_trim_param *pt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *pconfig &= ~HSPHY_CFG0_RTERM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *pconfig |= FIELD_PREP(HSPHY_CFG0_RTERM_MASK, pt->rterm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *pconfig &= ~HSPHY_CFG0_SEL_T_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *pconfig |= FIELD_PREP(HSPHY_CFG0_SEL_T_MASK, pt->sel_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *pconfig &= ~HSPHY_CFG0_HS_I_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *pconfig |= FIELD_PREP(HSPHY_CFG0_HS_I_MASK, pt->hs_i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int uniphier_u3hsphy_get_nvparam(struct uniphier_u3hsphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const char *name, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct nvmem_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cell = devm_nvmem_cell_get(priv->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (IS_ERR(cell))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return PTR_ERR(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) buf = nvmem_cell_read(cell, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (IS_ERR(buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return PTR_ERR(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *val = *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int uniphier_u3hsphy_get_nvparams(struct uniphier_u3hsphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct uniphier_u3hsphy_trim_param *pt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = uniphier_u3hsphy_get_nvparam(priv, "rterm", &pt->rterm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = uniphier_u3hsphy_get_nvparam(priv, "sel_t", &pt->sel_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = uniphier_u3hsphy_get_nvparam(priv, "hs_i", &pt->hs_i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int uniphier_u3hsphy_update_config(struct uniphier_u3hsphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 *pconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct uniphier_u3hsphy_trim_param trim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int ret, trimmed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (priv->data->trim_func) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = uniphier_u3hsphy_get_nvparams(priv, &trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * call trim_func only when trimming parameters that aren't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * all-zero can be acquired. All-zero parameters mean nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * has been written to nvmem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!ret && trim_param_is_valid(&trim)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) priv->data->trim_func(priv, pconfig, &trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) trimmed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_dbg(priv->dev, "can't get parameter from nvmem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* use default parameters without trimming values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!trimmed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *pconfig &= ~HSPHY_CFG0_HSDISC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *pconfig |= FIELD_PREP(HSPHY_CFG0_HSDISC_MASK, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void uniphier_u3hsphy_set_param(struct uniphier_u3hsphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const struct uniphier_u3hsphy_param *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 field_mask = GENMASK(p->field.msb, p->field.lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) val = readl(priv->base + HSPHY_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) val &= ~HSPHY_CFG1_ADR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val |= FIELD_PREP(HSPHY_CFG1_ADR_MASK, p->field.reg_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) | HSPHY_CFG1_ADR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel(val, priv->base + HSPHY_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val = readl(priv->base + HSPHY_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) val &= ~HSPHY_CFG1_ADR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel(val, priv->base + HSPHY_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val = readl(priv->base + HSPHY_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val &= ~FIELD_PREP(HSPHY_CFG1_DAT_MASK, field_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) data = field_mask & (p->value << p->field.lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val |= FIELD_PREP(HSPHY_CFG1_DAT_MASK, data) | HSPHY_CFG1_DAT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel(val, priv->base + HSPHY_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) val = readl(priv->base + HSPHY_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val &= ~HSPHY_CFG1_DAT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel(val, priv->base + HSPHY_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int uniphier_u3hsphy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = clk_prepare_enable(priv->clk_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) goto out_clk_ext_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = reset_control_deassert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (priv->vbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = regulator_enable(priv->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto out_rst_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) out_rst_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) reset_control_assert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) out_clk_ext_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clk_disable_unprepare(priv->clk_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int uniphier_u3hsphy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (priv->vbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) regulator_disable(priv->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) reset_control_assert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) clk_disable_unprepare(priv->clk_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int uniphier_u3hsphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 config0, config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = clk_prepare_enable(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = clk_prepare_enable(priv->clk_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = reset_control_deassert(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) goto out_clk_gio_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = reset_control_deassert(priv->rst_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto out_rst_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if ((priv->data->is_legacy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) || (!priv->data->config0 && !priv->data->config1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) config0 = priv->data->config0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) config1 = priv->data->config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = uniphier_u3hsphy_update_config(priv, &config0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) goto out_rst_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writel(config0, priv->base + HSPHY_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel(config1, priv->base + HSPHY_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) for (i = 0; i < priv->data->nparams; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) uniphier_u3hsphy_set_param(priv, &priv->data->param[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) out_rst_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) reset_control_assert(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) out_clk_gio_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clk_disable_unprepare(priv->clk_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) clk_disable_unprepare(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int uniphier_u3hsphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) reset_control_assert(priv->rst_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) reset_control_assert(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clk_disable_unprepare(priv->clk_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) clk_disable_unprepare(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct phy_ops uniphier_u3hsphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .init = uniphier_u3hsphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .exit = uniphier_u3hsphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .power_on = uniphier_u3hsphy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .power_off = uniphier_u3hsphy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int uniphier_u3hsphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct uniphier_u3hsphy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) priv->data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (WARN_ON(!priv->data ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) priv->data->nparams > MAX_PHY_PARAMS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!priv->data->is_legacy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) priv->clk = devm_clk_get(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) priv->clk_ext = devm_clk_get_optional(dev, "phy-ext");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (IS_ERR(priv->clk_ext))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return PTR_ERR(priv->clk_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) priv->rst = devm_reset_control_get_shared(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (IS_ERR(priv->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return PTR_ERR(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) priv->clk_parent_gio = devm_clk_get(dev, "gio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (IS_ERR(priv->clk_parent_gio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return PTR_ERR(priv->clk_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) priv->rst_parent_gio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) devm_reset_control_get_shared(dev, "gio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (IS_ERR(priv->rst_parent_gio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return PTR_ERR(priv->rst_parent_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) priv->clk_parent = devm_clk_get(dev, "link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (IS_ERR(priv->clk_parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return PTR_ERR(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) priv->rst_parent = devm_reset_control_get_shared(dev, "link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (IS_ERR(priv->rst_parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return PTR_ERR(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) priv->vbus = devm_regulator_get_optional(dev, "vbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (IS_ERR(priv->vbus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return PTR_ERR(priv->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) priv->vbus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) phy = devm_phy_create(dev, dev->of_node, &uniphier_u3hsphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (IS_ERR(phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) phy_set_drvdata(phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct uniphier_u3hsphy_soc_data uniphier_pro5_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .is_legacy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .nparams = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const struct uniphier_u3hsphy_soc_data uniphier_pxs2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .is_legacy = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .nparams = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { RX_CHK_SYNC, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { RX_SYNC_SEL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .is_legacy = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .nparams = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { RX_CHK_SYNC, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { RX_SYNC_SEL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { LS_SLEW, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { FS_LS_DRV, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .trim_func = uniphier_u3hsphy_trim_ld20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .config0 = 0x92316680,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .config1 = 0x00000106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const struct uniphier_u3hsphy_soc_data uniphier_pxs3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .is_legacy = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .nparams = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { RX_CHK_SYNC, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { RX_SYNC_SEL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .trim_func = uniphier_u3hsphy_trim_ld20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .config0 = 0x92316680,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .config1 = 0x00000106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct of_device_id uniphier_u3hsphy_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .compatible = "socionext,uniphier-pro5-usb3-hsphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .data = &uniphier_pro5_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .compatible = "socionext,uniphier-pxs2-usb3-hsphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .data = &uniphier_pxs2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .compatible = "socionext,uniphier-ld20-usb3-hsphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .data = &uniphier_ld20_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .compatible = "socionext,uniphier-pxs3-usb3-hsphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .data = &uniphier_pxs3_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_DEVICE_TABLE(of, uniphier_u3hsphy_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct platform_driver uniphier_u3hsphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .probe = uniphier_u3hsphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .name = "uniphier-usb3-hsphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .of_match_table = uniphier_u3hsphy_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) module_platform_driver(uniphier_u3hsphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MODULE_DESCRIPTION("UniPhier HS-PHY driver for USB3 controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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