^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2018, Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCL_PHY_CLKCTRL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PORT_SEL_MASK GENMASK(11, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCL_PHY_TEST_I 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TESTI_DAT_MASK GENMASK(13, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TESTI_ADR_MASK GENMASK(5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TESTI_WR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCL_PHY_TEST_O 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TESTO_DAT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCL_PHY_RESET 0x200c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* SG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SG_USBPCIESEL 0x590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SG_USBPCIESEL_PCIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCL_PHY_R00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCL_PHY_R06 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RX_EQ_ADJ GENMASK(5, 0) /* EQ adjustment value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RX_EQ_ADJ_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCL_PHY_R26 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VCO_CTRL GENMASK(7, 4) /* Tx VCO adjustment value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VCO_CTRL_INIT_VAL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct uniphier_pciephy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *clk, *clk_gio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct reset_control *rst, *rst_gio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const struct uniphier_pciephy_soc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct uniphier_pciephy_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bool is_legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void (*set_phymode)(struct regmap *regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* need to read TESTO twice after accessing TESTI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(data, priv->base + PCL_PHY_TEST_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) readl(priv->base + PCL_PHY_TEST_O);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) readl(priv->base + PCL_PHY_TEST_O);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 reg, u32 mask, u32 param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* read previous data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) val = FIELD_PREP(TESTI_DAT_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) val |= FIELD_PREP(TESTI_ADR_MASK, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) uniphier_pciephy_testio_write(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val = readl(priv->base + PCL_PHY_TEST_O) & TESTO_DAT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* update value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) val |= mask & param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val = FIELD_PREP(TESTI_DAT_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val |= FIELD_PREP(TESTI_ADR_MASK, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) uniphier_pciephy_testio_write(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) uniphier_pciephy_testio_write(priv, val | TESTI_WR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) uniphier_pciephy_testio_write(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* read current data as dummy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val = FIELD_PREP(TESTI_DAT_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) val |= FIELD_PREP(TESTI_ADR_MASK, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) uniphier_pciephy_testio_write(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) readl(priv->base + PCL_PHY_TEST_O);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void uniphier_pciephy_assert(struct uniphier_pciephy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val = readl(priv->base + PCL_PHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val &= ~PCL_PHY_RESET_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val |= PCL_PHY_RESET_N_MNMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writel(val, priv->base + PCL_PHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val = readl(priv->base + PCL_PHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val |= PCL_PHY_RESET_N_MNMODE | PCL_PHY_RESET_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel(val, priv->base + PCL_PHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int uniphier_pciephy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = clk_prepare_enable(priv->clk_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ret = reset_control_deassert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) goto out_clk_gio_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = reset_control_deassert(priv->rst_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) goto out_rst_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* support only 1 port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val = readl(priv->base + PCL_PHY_CLKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val &= ~PORT_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) val |= PORT_SEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(val, priv->base + PCL_PHY_CLKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* legacy controller doesn't have phy_reset and parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (priv->data->is_legacy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) uniphier_pciephy_set_param(priv, PCL_PHY_R00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) RX_EQ_ADJ_EN, RX_EQ_ADJ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) uniphier_pciephy_set_param(priv, PCL_PHY_R06, RX_EQ_ADJ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) uniphier_pciephy_set_param(priv, PCL_PHY_R26, VCO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) usleep_range(1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) uniphier_pciephy_deassert(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) usleep_range(1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) out_rst_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) reset_control_assert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) out_clk_gio_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clk_disable_unprepare(priv->clk_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int uniphier_pciephy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!priv->data->is_legacy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) uniphier_pciephy_assert(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) reset_control_assert(priv->rst_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) reset_control_assert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clk_disable_unprepare(priv->clk_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct phy_ops uniphier_pciephy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .init = uniphier_pciephy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .exit = uniphier_pciephy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int uniphier_pciephy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct uniphier_pciephy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) priv->data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (WARN_ON(!priv->data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (priv->data->is_legacy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) priv->clk_gio = devm_clk_get(dev, "gio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (IS_ERR(priv->clk_gio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return PTR_ERR(priv->clk_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) priv->rst_gio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) devm_reset_control_get_shared(dev, "gio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (IS_ERR(priv->rst_gio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return PTR_ERR(priv->rst_gio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) priv->clk = devm_clk_get(dev, "link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) priv->rst = devm_reset_control_get_shared(dev, "link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (IS_ERR(priv->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return PTR_ERR(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) priv->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) priv->rst = devm_reset_control_get_shared(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (IS_ERR(priv->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return PTR_ERR(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (IS_ERR(phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "socionext,syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!IS_ERR(regmap) && priv->data->set_phymode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) priv->data->set_phymode(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) phy_set_drvdata(phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void uniphier_pciephy_ld20_setmode(struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) regmap_update_bits(regmap, SG_USBPCIESEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct uniphier_pciephy_soc_data uniphier_pro5_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .is_legacy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct uniphier_pciephy_soc_data uniphier_ld20_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .is_legacy = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .set_phymode = uniphier_pciephy_ld20_setmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .is_legacy = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct of_device_id uniphier_pciephy_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .compatible = "socionext,uniphier-pro5-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .data = &uniphier_pro5_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .compatible = "socionext,uniphier-ld20-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .data = &uniphier_ld20_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .compatible = "socionext,uniphier-pxs3-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .data = &uniphier_pxs3_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_DEVICE_TABLE(of, uniphier_pciephy_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct platform_driver uniphier_pciephy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .probe = uniphier_pciephy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .name = "uniphier-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .of_match_table = uniphier_pciephy_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) module_platform_driver(uniphier_pciephy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_DESCRIPTION("UniPhier PHY driver for PCIe controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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