^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * phy-uniphier-ahci.c - PHY driver for UniPhier AHCI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2016-2020, Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct uniphier_ahciphy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk *clk, *clk_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct reset_control *rst, *rst_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const struct uniphier_ahciphy_soc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct uniphier_ahciphy_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int (*init)(struct uniphier_ahciphy_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int (*power_on)(struct uniphier_ahciphy_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int (*power_off)(struct uniphier_ahciphy_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) bool is_ready_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) bool is_phy_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* for PXs2/PXs3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CKCTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CKCTRL_P0_READY BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CKCTRL_P0_RESET BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CKCTRL_REF_SSP_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TXCTRL0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TXCTRL0_AMP_G3_MASK GENMASK(22, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TXCTRL0_AMP_G2_MASK GENMASK(14, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TXCTRL0_AMP_G1_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TXCTRL1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TXCTRL1_DEEMPH_G3_MASK GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TXCTRL1_DEEMPH_G2_MASK GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TXCTRL1_DEEMPH_G1_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RXCTRL 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RXCTRL_LOS_LVL_MASK GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RXCTRL_LOS_BIAS_MASK GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RXCTRL_RX_EQ_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void uniphier_ahciphy_pxs2_enable(struct uniphier_ahciphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) val = readl(priv->base + CKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) val |= CKCTRL_REF_SSP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) writel(val, priv->base + CKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) val &= ~CKCTRL_P0_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel(val, priv->base + CKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) val |= CKCTRL_P0_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) writel(val, priv->base + CKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) val &= ~CKCTRL_REF_SSP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel(val, priv->base + CKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int uniphier_ahciphy_pxs2_power_on(struct uniphier_ahciphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) uniphier_ahciphy_pxs2_enable(priv, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* wait until PLL is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (priv->data->is_ready_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = readl_poll_timeout(priv->base + CKCTRL, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (val & CKCTRL_P0_READY), 200, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = readl_poll_timeout(priv->base + CKCTRL, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) !(val & CKCTRL_P0_READY), 200, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dev_err(priv->dev, "Failed to check whether PHY PLL is ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) uniphier_ahciphy_pxs2_enable(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int uniphier_ahciphy_pxs2_power_off(struct uniphier_ahciphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) uniphier_ahciphy_pxs2_enable(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int uniphier_ahciphy_pxs3_init(struct uniphier_ahciphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* setup port parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) val = readl(priv->base + TXCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val &= ~TXCTRL0_AMP_G3_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val |= FIELD_PREP(TXCTRL0_AMP_G3_MASK, 0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val &= ~TXCTRL0_AMP_G2_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) val |= FIELD_PREP(TXCTRL0_AMP_G2_MASK, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val &= ~TXCTRL0_AMP_G1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val |= FIELD_PREP(TXCTRL0_AMP_G1_MASK, 0x42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(val, priv->base + TXCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val = readl(priv->base + TXCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val &= ~TXCTRL1_DEEMPH_G3_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) val |= FIELD_PREP(TXCTRL1_DEEMPH_G3_MASK, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val &= ~TXCTRL1_DEEMPH_G2_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val |= FIELD_PREP(TXCTRL1_DEEMPH_G2_MASK, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) val &= ~TXCTRL1_DEEMPH_G1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val |= FIELD_PREP(TXCTRL1_DEEMPH_G1_MASK, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val = readl(priv->base + RXCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val &= ~RXCTRL_LOS_LVL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val |= FIELD_PREP(RXCTRL_LOS_LVL_MASK, 0x9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val &= ~RXCTRL_LOS_BIAS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) val |= FIELD_PREP(RXCTRL_LOS_BIAS_MASK, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) val &= ~RXCTRL_RX_EQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) val |= FIELD_PREP(RXCTRL_RX_EQ_MASK, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* dummy read 25 times to make a wait time for the phy to stabilize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (i = 0; i < 25; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) readl(priv->base + CKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int uniphier_ahciphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = clk_prepare_enable(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = reset_control_deassert(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (priv->data->init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = priv->data->init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) goto out_rst_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) out_rst_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) reset_control_assert(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk_disable_unprepare(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int uniphier_ahciphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) reset_control_assert(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clk_disable_unprepare(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int uniphier_ahciphy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = reset_control_deassert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (priv->data->power_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = priv->data->power_on(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto out_reset_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) out_reset_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) reset_control_assert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int uniphier_ahciphy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (priv->data->power_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = priv->data->power_off(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reset_control_assert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct phy_ops uniphier_ahciphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .init = uniphier_ahciphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .exit = uniphier_ahciphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .power_on = uniphier_ahciphy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .power_off = uniphier_ahciphy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int uniphier_ahciphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct uniphier_ahciphy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) priv->data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (WARN_ON(!priv->data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) priv->clk_parent = devm_clk_get(dev, "link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (IS_ERR(priv->clk_parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return PTR_ERR(priv->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (priv->data->is_phy_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) priv->clk = devm_clk_get(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) priv->rst_parent = devm_reset_control_get_shared(dev, "link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (IS_ERR(priv->rst_parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return PTR_ERR(priv->rst_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) priv->rst = devm_reset_control_get_shared(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (IS_ERR(priv->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return PTR_ERR(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) phy = devm_phy_create(dev, dev->of_node, &uniphier_ahciphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_err(dev, "failed to create phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) phy_set_drvdata(phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (IS_ERR(phy_provider))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const struct uniphier_ahciphy_soc_data uniphier_pxs2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .power_on = uniphier_ahciphy_pxs2_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .power_off = uniphier_ahciphy_pxs2_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .is_ready_high = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .is_phy_clk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct uniphier_ahciphy_soc_data uniphier_pxs3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .init = uniphier_ahciphy_pxs3_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .power_on = uniphier_ahciphy_pxs2_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .power_off = uniphier_ahciphy_pxs2_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .is_ready_high = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .is_phy_clk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct of_device_id uniphier_ahciphy_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .compatible = "socionext,uniphier-pxs2-ahci-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .data = &uniphier_pxs2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .compatible = "socionext,uniphier-pxs3-ahci-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .data = &uniphier_pxs3_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MODULE_DEVICE_TABLE(of, uniphier_ahciphy_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct platform_driver uniphier_ahciphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .probe = uniphier_ahciphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .name = "uniphier-ahci-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .of_match_table = uniphier_ahciphy_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) module_platform_driver(uniphier_ahciphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MODULE_DESCRIPTION("UniPhier PHY driver for AHCI controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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