^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * UFS PHY driver for Samsung SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Seungwon Jeon <essuuj@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Alim Akhtar <alim.akhtar@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "phy-samsung-ufs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define for_each_phy_lane(phy, i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) for (i = 0; i < (phy)->lane_cnt; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define for_each_phy_cfg(cfg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) for (; (cfg)->id; (cfg)++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PHY_DEF_LANE_CNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) const struct samsung_ufs_phy_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum {LANE_0, LANE_1}; /* lane index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) switch (lane) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) case LANE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) writel(cfg->val, (phy)->reg_pma + cfg->off_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case LANE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (cfg->id == PHY_TRSV_BLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) writel(cfg->val, (phy)->reg_pma + cfg->off_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const unsigned int timeout_us = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const unsigned int sleep_us = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) err = readl_poll_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_err(ufs_phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "failed to get phy pll lock acquisition %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) err = readl_poll_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dev_err(ufs_phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "failed to get phy cdr lock acquisition %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int samsung_ufs_phy_calibrate(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const struct samsung_ufs_phy_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_err(ufs_phy->dev, "invalid phy config index %d\n", ufs_phy->ufs_phy_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cfg = cfgs[ufs_phy->ufs_phy_state];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for_each_phy_cfg(cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) for_each_phy_lane(ufs_phy, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) samsung_ufs_phy_config(ufs_phy, cfg, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) err = samsung_ufs_phy_wait_for_lock_acq(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * In Samsung ufshci, PHY need to be calibrated at different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * stages / state mainly before Linkstartup, after Linkstartup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * before power mode change and after power mode change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Below state machine to make sure to calibrate PHY in each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * state. Here after configuring PHY in a given state, will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * change the state to next state so that next state phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * calibration value can be programed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) switch (ufs_phy->ufs_phy_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case CFG_PRE_INIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ufs_phy->ufs_phy_state = CFG_POST_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case CFG_POST_INIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case CFG_PRE_PWR_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ufs_phy->ufs_phy_state = CFG_POST_PWR_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case CFG_POST_PWR_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Change back to INIT state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ufs_phy->ufs_phy_state = CFG_PRE_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_err(ufs_phy->dev, "wrong state for phy calibration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (IS_ERR(phy->tx0_symbol_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return PTR_ERR(phy->tx0_symbol_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (IS_ERR(phy->rx0_symbol_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return PTR_ERR(phy->rx0_symbol_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (IS_ERR(phy->rx1_symbol_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return PTR_ERR(phy->rx1_symbol_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = clk_prepare_enable(phy->tx0_symbol_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = clk_prepare_enable(phy->rx0_symbol_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto out_disable_tx0_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = clk_prepare_enable(phy->rx1_symbol_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) goto out_disable_rx0_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) out_disable_rx0_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clk_disable_unprepare(phy->rx0_symbol_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) out_disable_tx0_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clk_disable_unprepare(phy->tx0_symbol_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) phy->ref_clk = devm_clk_get(phy->dev, "ref_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (IS_ERR(phy->ref_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(phy->dev, "failed to get ref_clk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = clk_prepare_enable(phy->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dev_err(phy->dev, "%s: ref_clk enable failed %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_dbg(phy->dev, "UFS MPHY ref_clk_rate = %ld\n", clk_get_rate(phy->ref_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int samsung_ufs_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ss_phy->lane_cnt = phy->attrs.bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ss_phy->ufs_phy_state = CFG_PRE_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ss_phy->drvdata->has_symbol_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = samsung_ufs_phy_symbol_clk_init(ss_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_err(ss_phy->dev, "failed to set ufs phy symbol clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = samsung_ufs_phy_clks_init(ss_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(ss_phy->dev, "failed to set ufs phy clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = samsung_ufs_phy_calibrate(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_err(ss_phy->dev, "ufs phy calibration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int samsung_ufs_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) samsung_ufs_phy_ctrl_isol(ss_phy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int samsung_ufs_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) samsung_ufs_phy_ctrl_isol(ss_phy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int samsung_ufs_phy_set_mode(struct phy *generic_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) enum phy_mode mode, int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ss_phy->mode = PHY_MODE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (mode > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ss_phy->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int samsung_ufs_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clk_disable_unprepare(ss_phy->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ss_phy->drvdata->has_symbol_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) clk_disable_unprepare(ss_phy->tx0_symbol_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) clk_disable_unprepare(ss_phy->rx0_symbol_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clk_disable_unprepare(ss_phy->rx1_symbol_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct phy_ops samsung_ufs_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .init = samsung_ufs_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .exit = samsung_ufs_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .power_on = samsung_ufs_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .power_off = samsung_ufs_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .calibrate = samsung_ufs_phy_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .set_mode = samsung_ufs_phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct of_device_id samsung_ufs_phy_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int samsung_ufs_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct samsung_ufs_phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct phy *gen_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) const struct samsung_ufs_phy_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) match = of_match_node(samsung_ufs_phy_match, dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_err(dev, "failed to get match_node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) phy->reg_pma = devm_platform_ioremap_resource_byname(pdev, "phy-pma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (IS_ERR(phy->reg_pma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) err = PTR_ERR(phy->reg_pma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) phy->reg_pmu = syscon_regmap_lookup_by_phandle(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev->of_node, "samsung,pmu-syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (IS_ERR(phy->reg_pmu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) err = PTR_ERR(phy->reg_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_err(dev, "failed syscon remap for pmu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) gen_phy = devm_phy_create(dev, NULL, &samsung_ufs_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (IS_ERR(gen_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) err = PTR_ERR(gen_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_err(dev, "failed to create PHY for ufs-phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) drvdata = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) phy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) phy->drvdata = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) phy->cfg = (struct samsung_ufs_phy_cfg **)drvdata->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) phy->isol = &drvdata->isol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) phy->lane_cnt = PHY_DEF_LANE_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) phy_set_drvdata(gen_phy, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) err = PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_err(dev, "failed to register phy-provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct of_device_id samsung_ufs_phy_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .compatible = "samsung,exynos7-ufs-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .data = &exynos7_ufs_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_DEVICE_TABLE(of, samsung_ufs_phy_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct platform_driver samsung_ufs_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .probe = samsung_ufs_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .name = "samsung-ufs-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .of_match_table = samsung_ufs_phy_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) module_platform_driver(samsung_ufs_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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