^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors: Kamil Debski <k.debski@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "phy-samsung-usb2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Exynos USB PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* PHY power control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S5PV210_UPHYPWR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S5PV210_UPHYPWR_PHY0_SUSPEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S5PV210_UPHYPWR_PHY0_PWR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S5PV210_UPHYPWR_PHY0_OTG_PWR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S5PV210_UPHYPWR_PHY0 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) S5PV210_UPHYPWR_PHY0_SUSPEND | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) S5PV210_UPHYPWR_PHY0_PWR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) S5PV210_UPHYPWR_PHY0_OTG_PWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S5PV210_UPHYPWR_PHY1_SUSPEND BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S5PV210_UPHYPWR_PHY1_PWR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S5PV210_UPHYPWR_PHY1 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) S5PV210_UPHYPWR_PHY1_SUSPEND | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) S5PV210_UPHYPWR_PHY1_PWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* PHY clock control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S5PV210_UPHYCLK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S5PV210_UPHYCLK_PHYFSEL_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S5PV210_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S5PV210_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S5PV210_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S5PV210_UPHYCLK_PHY0_ID_PULLUP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S5PV210_UPHYCLK_PHY0_COMMON_ON BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S5PV210_UPHYCLK_PHY1_COMMON_ON BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* PHY reset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S5PV210_UPHYRST 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S5PV210_URSTCON_PHY0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S5PV210_URSTCON_OTG_HLINK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S5PV210_URSTCON_OTG_PHYLINK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S5PV210_URSTCON_PHY1_ALL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S5PV210_URSTCON_HOST_LINK_ALL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Isolation, configured in the power management unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S5PV210_USB_ISOL_OFFSET 0x680c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S5PV210_USB_ISOL_DEVICE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S5PV210_USB_ISOL_HOST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum s5pv210_phy_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) S5PV210_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) S5PV210_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) S5PV210_NUM_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * s5pv210_rate_to_clk() converts the supplied clock rate to the value that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * can be written to the phy register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int s5pv210_rate_to_clk(unsigned long rate, u32 *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) case 12 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *reg = S5PV210_UPHYCLK_PHYFSEL_12MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case 24 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *reg = S5PV210_UPHYCLK_PHYFSEL_24MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case 48 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *reg = S5PV210_UPHYCLK_PHYFSEL_48MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void s5pv210_isol(struct samsung_usb2_phy_instance *inst, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) switch (inst->cfg->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case S5PV210_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mask = S5PV210_USB_ISOL_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case S5PV210_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mask = S5PV210_USB_ISOL_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) regmap_update_bits(drv->reg_pmu, S5PV210_USB_ISOL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mask, on ? 0 : mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 rstbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 phypwr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) switch (inst->cfg->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case S5PV210_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) phypwr = S5PV210_UPHYPWR_PHY0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) rstbits = S5PV210_URSTCON_PHY0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case S5PV210_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) phypwr = S5PV210_UPHYPWR_PHY1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rstbits = S5PV210_URSTCON_PHY1_ALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) S5PV210_URSTCON_HOST_LINK_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writel(drv->ref_reg_val, drv->reg_phy + S5PV210_UPHYCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pwr &= ~phypwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) rst = readl(drv->reg_phy + S5PV210_UPHYRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rst |= rstbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writel(rst, drv->reg_phy + S5PV210_UPHYRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) rst &= ~rstbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel(rst, drv->reg_phy + S5PV210_UPHYRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* The following delay is necessary for the reset sequence to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) udelay(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pwr |= phypwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int s5pv210_power_on(struct samsung_usb2_phy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) s5pv210_isol(inst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) s5pv210_phy_pwr(inst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int s5pv210_power_off(struct samsung_usb2_phy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) s5pv210_phy_pwr(inst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) s5pv210_isol(inst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct samsung_usb2_common_phy s5pv210_phys[S5PV210_NUM_PHYS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [S5PV210_DEVICE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .label = "device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .id = S5PV210_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .power_on = s5pv210_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .power_off = s5pv210_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [S5PV210_HOST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .label = "host",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .id = S5PV210_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .power_on = s5pv210_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .power_off = s5pv210_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) const struct samsung_usb2_phy_config s5pv210_usb2_phy_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .num_phys = ARRAY_SIZE(s5pv210_phys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .phys = s5pv210_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .rate_to_clk = s5pv210_rate_to_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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