^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * UFS PHY driver data for Samsung EXYNOS7 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _PHY_EXYNOS7_UFS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _PHY_EXYNOS7_UFS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "phy-samsung-ufs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Calibration for phy initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) END_UFS_PHY_CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Calibration for HS mode series A/B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Setting order: 1st(0x16, 2nd(0x15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) END_UFS_PHY_CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Calibration for HS mode series A/B atfer PMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) END_UFS_PHY_CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [CFG_PRE_INIT] = exynos7_pre_init_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .cfg = exynos7_ufs_phy_cfgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .isol = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .has_symbol_clk = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif /* _PHY_EXYNOS7_UFS_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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