^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Kamil Debski <k.debski@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "phy-samsung-usb2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Exynos USB PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define EXYNOS_5250_REFCLKSEL_CRYSTAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EXYNOS_5250_REFCLKSEL_XO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EXYNOS_5250_REFCLKSEL_CLKCORE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EXYNOS_5250_FSEL_9MHZ6 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EXYNOS_5250_FSEL_10MHZ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EXYNOS_5250_FSEL_12MHZ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EXYNOS_5250_FSEL_19MHZ2 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EXYNOS_5250_FSEL_20MHZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EXYNOS_5250_FSEL_24MHZ 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EXYNOS_5250_FSEL_50MHZ 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Normal host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EXYNOS_5250_HOSTPHYCTRL0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) (0x3 << EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (0x7 << EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNIN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_MASK (0x3 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_DUAL (0x0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ID0 (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ANALOGTEST (0x2 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EXYNOS_5250_HOSTPHYCTRL0_SIDDQ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EXYNOS_5250_HOSTPHYCTRL0_WORDINTERFACE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* HSIC0 & HSIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EXYNOS_5250_HSICPHYCTRL1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EXYNOS_5250_HSICPHYCTRL2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_MASK (0x3 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_DEFAULT (0x2 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_MASK (0x7f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_12 (0x24 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_15 (0x1c << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_16 (0x1a << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_19_2 (0x15 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_20 (0x14 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EXYNOS_5250_HSICPHYCTRLX_SIDDQ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EXYNOS_5250_HSICPHYCTRLX_FORCESLEEP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EXYNOS_5250_HSICPHYCTRLX_FORCESUSPEND BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EXYNOS_5250_HSICPHYCTRLX_WORDINTERFACE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EXYNOS_5250_HSICPHYCTRLX_UTMISWRST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EXYNOS_5250_HSICPHYCTRLX_PHYSWRST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* EHCI control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EXYNOS_5250_HOSTEHCICTRL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EXYNOS_5250_HOSTEHCICTRL_ENAINCR4 BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EXYNOS_5250_HOSTEHCICTRL_ENAINCR8 BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EXYNOS_5250_HOSTEHCICTRL_ENAINCR16 BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EXYNOS_5250_HOSTEHCICTRL_AUTOPPDONOVRCUREN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) (0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL2_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) (0x1 << EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EXYNOS_5250_HOSTEHCICTRL_SIMULATIONMODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* OHCI control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define EXYNOS_5250_HOSTOHCICTRL 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (0x3ff << EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVALEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* USBOTG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define EXYNOS_5250_USBOTGSYS 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define EXYNOS_5250_USBOTGSYS_PHY_SW_RST BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) (0x3 << EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EXYNOS_5250_USBOTGSYS_ID_PULLUP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EXYNOS_5250_USBOTGSYS_COMMON_ON BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EXYNOS_5250_USBOTGSYS_FSEL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define EXYNOS_5250_USBOTGSYS_FSEL_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (0x3 << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define EXYNOS_5250_USBOTGSYS_FORCE_SLEEP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define EXYNOS_5250_USBOTGSYS_OTGDISABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Isolation, configured in the power management unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EXYNOS_5250_USB_ISOL_OTG_OFFSET 0x704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EXYNOS_5250_USB_ISOL_OTG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define EXYNOS_5250_USB_ISOL_HOST_OFFSET 0x708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EXYNOS_5250_USB_ISOL_HOST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Mode swtich register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EXYNOS_5250_MODE_SWITCH_OFFSET 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EXYNOS_5250_MODE_SWITCH_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EXYNOS_5250_MODE_SWITCH_DEVICE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define EXYNOS_5250_MODE_SWITCH_HOST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) enum exynos4x12_phy_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) EXYNOS5250_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) EXYNOS5250_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) EXYNOS5250_HSIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) EXYNOS5250_HSIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) EXYNOS5250_NUM_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * exynos5250_rate_to_clk() converts the supplied clock rate to the value that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * can be written to the phy register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int exynos5250_rate_to_clk(unsigned long rate, u32 *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* EXYNOS_5250_FSEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case 9600 * KHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *reg = EXYNOS_5250_FSEL_9MHZ6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case 10 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *reg = EXYNOS_5250_FSEL_10MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case 12 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *reg = EXYNOS_5250_FSEL_12MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case 19200 * KHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *reg = EXYNOS_5250_FSEL_19MHZ2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case 20 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *reg = EXYNOS_5250_FSEL_20MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case 24 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *reg = EXYNOS_5250_FSEL_24MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case 50 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *reg = EXYNOS_5250_FSEL_50MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void exynos5250_isol(struct samsung_usb2_phy_instance *inst, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) switch (inst->cfg->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case EXYNOS5250_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) offset = EXYNOS_5250_USB_ISOL_OTG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mask = EXYNOS_5250_USB_ISOL_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case EXYNOS5250_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) offset = EXYNOS_5250_USB_ISOL_HOST_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mask = EXYNOS_5250_USB_ISOL_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 ehci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 ohci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 hsic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) switch (inst->cfg->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case EXYNOS5250_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) regmap_update_bits(drv->reg_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) EXYNOS_5250_MODE_SWITCH_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) EXYNOS_5250_MODE_SWITCH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) EXYNOS_5250_MODE_SWITCH_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* OTG configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* The clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) otg &= ~EXYNOS_5250_USBOTGSYS_FSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) otg |= drv->ref_reg_val << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) otg &= ~(EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) EXYNOS_5250_USBOTGSYS_FORCE_SLEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) otg |= EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) EXYNOS_5250_USBOTGSYS_OTGDISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Ref clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) otg &= ~EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) otg |= EXYNOS_5250_REFCLKSEL_CLKCORE <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) otg &= ~(EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) EXYNOS_5250_USBOTGSYS_OTGDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case EXYNOS5250_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case EXYNOS5250_HSIC0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case EXYNOS5250_HSIC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Host registers configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* The clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ctrl0 &= ~EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ctrl0 |= drv->ref_reg_val <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) EXYNOS_5250_HOSTPHYCTRL0_SIDDQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ctrl0 |= EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* OTG configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* The clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) otg &= ~EXYNOS_5250_USBOTGSYS_FSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) otg |= drv->ref_reg_val << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) otg &= ~(EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) EXYNOS_5250_USBOTGSYS_FORCE_SLEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) otg |= EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) EXYNOS_5250_USBOTGSYS_OTGDISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Ref clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) otg &= ~EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) otg |= EXYNOS_5250_REFCLKSEL_CLKCORE <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) otg &= ~(EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* HSIC phy configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) hsic = (EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_12 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_DEFAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) EXYNOS_5250_HSICPHYCTRLX_PHYSWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) hsic &= ~EXYNOS_5250_HSICPHYCTRLX_PHYSWRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* The following delay is necessary for the reset sequence to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) udelay(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Enable EHCI DMA burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ehci = readl(drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ehci |= EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) EXYNOS_5250_HOSTEHCICTRL_ENAINCR4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) EXYNOS_5250_HOSTEHCICTRL_ENAINCR8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) EXYNOS_5250_HOSTEHCICTRL_ENAINCR16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) writel(ehci, drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* OHCI settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ohci = readl(drv->reg_phy + EXYNOS_5250_HOSTOHCICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Following code is based on the old driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ohci |= 0x1 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) writel(ohci, drv->reg_phy + EXYNOS_5250_HOSTOHCICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) exynos5250_isol(inst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int exynos5250_power_off(struct samsung_usb2_phy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 hsic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) exynos5250_isol(inst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) switch (inst->cfg->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case EXYNOS5250_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) otg |= (EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) EXYNOS_5250_USBOTGSYS_FORCE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case EXYNOS5250_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ctrl0 |= (EXYNOS_5250_HOSTPHYCTRL0_SIDDQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case EXYNOS5250_HSIC0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case EXYNOS5250_HSIC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) hsic = (EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_12 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_DEFAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) EXYNOS_5250_HSICPHYCTRLX_SIDDQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) EXYNOS_5250_HSICPHYCTRLX_FORCESLEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) EXYNOS_5250_HSICPHYCTRLX_FORCESUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct samsung_usb2_common_phy exynos5250_phys[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .label = "device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .id = EXYNOS5250_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .power_on = exynos5250_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .power_off = exynos5250_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .label = "host",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .id = EXYNOS5250_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .power_on = exynos5250_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .power_off = exynos5250_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .label = "hsic0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .id = EXYNOS5250_HSIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .power_on = exynos5250_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .power_off = exynos5250_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .label = "hsic1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .id = EXYNOS5250_HSIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .power_on = exynos5250_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .power_off = exynos5250_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) const struct samsung_usb2_phy_config exynos5250_usb2_phy_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .has_mode_switch = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .num_phys = EXYNOS5250_NUM_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .phys = exynos5250_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .rate_to_clk = exynos5250_rate_to_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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