^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Samsung SATA SerDes(PHY) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors: Girish K S <ks.giri@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SATAPHY_CONTROL_OFFSET 0x0724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EXYNOS5_SATAPHY_PMU_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EXYNOS5_SATA_RESET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RESET_GLOBAL_RST_N BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RESET_CMN_RST_N BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RESET_CMN_BLOCK_RST_N BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RESET_CMN_I2C_RST_N BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RESET_TX_RX_PIPE_RST_N BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RESET_TX_RX_BLOCK_RST_N BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RESET_TX_RX_I2C_RST_N (BIT(6) | BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LINK_RESET 0xf0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EXYNOS5_SATA_MODE0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SATA_SPD_GEN3 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EXYNOS5_SATA_CTRL0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CTRL0_P0_PHY_CALIBRATED_SEL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CTRL0_P0_PHY_CALIBRATED BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EXYNOS5_SATA_PHSATA_CTRLM 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PHCTRLM_REF_RATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PHCTRLM_HIGH_SPEED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EXYNOS5_SATA_PHSATA_STATM 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PHSTATM_PLL_LOCKED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PHY_PLL_TIMEOUT (usecs_to_jiffies(1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct exynos_sata_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk *phyclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct regmap *pmureg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long timeout = jiffies + PHY_PLL_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if ((readl(base + reg) & checkbit) == status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int exynos_sata_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) EXYNOS5_SATAPHY_PMU_ENABLE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int exynos_sata_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) EXYNOS5_SATAPHY_PMU_ENABLE, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int exynos_sata_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 buf[] = { 0x3a, 0x0b };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) EXYNOS5_SATAPHY_PMU_ENABLE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_err(&sata_phy->phy->dev, "phy init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) val |= RESET_GLOBAL_RST_N | RESET_CMN_RST_N | RESET_CMN_BLOCK_RST_N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) | RESET_CMN_I2C_RST_N | RESET_TX_RX_PIPE_RST_N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) | RESET_TX_RX_BLOCK_RST_N | RESET_TX_RX_I2C_RST_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) val |= LINK_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) val |= RESET_CMN_RST_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val &= ~PHCTRLM_REF_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* High speed enable for Gen3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val |= PHCTRLM_HIGH_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val = readl(sata_phy->regs + EXYNOS5_SATA_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val = readl(sata_phy->regs + EXYNOS5_SATA_MODE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) val |= SATA_SPD_GEN3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = i2c_master_send(sata_phy->client, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* release cmu reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val &= ~RESET_CMN_RST_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val |= RESET_CMN_RST_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = wait_for_reg_status(sata_phy->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) EXYNOS5_SATA_PHSATA_STATM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PHSTATM_PLL_LOCKED, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(&sata_phy->phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "PHY PLL locking failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct phy_ops exynos_sata_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .init = exynos_sata_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .power_on = exynos_sata_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .power_off = exynos_sata_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int exynos_sata_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct exynos_sata_phy *sata_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!sata_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sata_phy->regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (IS_ERR(sata_phy->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return PTR_ERR(sata_phy->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sata_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "samsung,syscon-phandle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (IS_ERR(sata_phy->pmureg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_err(dev, "syscon regmap lookup failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return PTR_ERR(sata_phy->pmureg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) node = of_parse_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "samsung,exynos-sataphy-i2c-phandle", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) sata_phy->client = of_find_i2c_device_by_node(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!sata_phy->client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_set_drvdata(dev, sata_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (IS_ERR(sata_phy->phyclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(dev, "failed to get clk for PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return PTR_ERR(sata_phy->phyclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = clk_prepare_enable(sata_phy->phyclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_err(dev, "failed to enable source clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) sata_phy->phy = devm_phy_create(dev, NULL, &exynos_sata_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (IS_ERR(sata_phy->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) clk_disable_unprepare(sata_phy->phyclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return PTR_ERR(sata_phy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) phy_set_drvdata(sata_phy->phy, sata_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) phy_provider = devm_of_phy_provider_register(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clk_disable_unprepare(sata_phy->phyclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const struct of_device_id exynos_sata_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { .compatible = "samsung,exynos5250-sata-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MODULE_DEVICE_TABLE(of, exynos_sata_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct platform_driver exynos_sata_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .probe = exynos_sata_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .of_match_table = exynos_sata_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .name = "samsung,sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) module_platform_driver(exynos_sata_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_DESCRIPTION("Samsung SerDes PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_AUTHOR("Yuvaraj C D <yuvaraj.cd@samsung.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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