Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Kamil Debski <k.debski@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "phy-samsung-usb2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* Exynos USB PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* PHY power control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define EXYNOS_4x12_UPHYPWR			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define EXYNOS_4x12_UPHYPWR_PHY0_PWR		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define EXYNOS_4x12_UPHYPWR_PHY0_SLEEP		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define EXYNOS_4x12_UPHYPWR_PHY0 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	EXYNOS_4x12_UPHYPWR_PHY0_PWR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	EXYNOS_4x12_UPHYPWR_PHY0_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define EXYNOS_4x12_UPHYPWR_PHY1_PWR		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define EXYNOS_4x12_UPHYPWR_PHY1_SLEEP		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define EXYNOS_4x12_UPHYPWR_PHY1 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	EXYNOS_4x12_UPHYPWR_PHY1_PWR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	EXYNOS_4x12_UPHYPWR_PHY1_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define EXYNOS_4x12_UPHYPWR_HSIC0_PWR		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define EXYNOS_4x12_UPHYPWR_HSIC0 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	EXYNOS_4x12_UPHYPWR_HSIC0_PWR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define EXYNOS_4x12_UPHYPWR_HSIC1_SUSPEND	BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define EXYNOS_4x12_UPHYPWR_HSIC1_PWR		BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define EXYNOS_4x12_UPHYPWR_HSIC1_SLEEP		BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define EXYNOS_4x12_UPHYPWR_HSIC1 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	EXYNOS_4x12_UPHYPWR_HSIC1_SUSPEND | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	EXYNOS_4x12_UPHYPWR_HSIC1_PWR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	EXYNOS_4x12_UPHYPWR_HSIC1_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* PHY clock control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define EXYNOS_4x12_UPHYCLK			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK	(0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6	(0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ	(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2	(0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ	(0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ	(0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ	(0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define EXYNOS_3250_UPHYCLK_REFCLKSEL		(0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define EXYNOS_4x12_UPHYCLK_PHY0_ID_PULLUP	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define EXYNOS_4x12_UPHYCLK_PHY0_COMMON_ON	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_MASK	(0x7f << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_OFFSET  10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_12MHZ	(0x24 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_15MHZ	(0x1c << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_16MHZ	(0x1a << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_19MHZ2	(0x15 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_20MHZ	(0x14 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* PHY reset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define EXYNOS_4x12_UPHYRST			0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define EXYNOS_4x12_URSTCON_PHY0		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define EXYNOS_4x12_URSTCON_OTG_HLINK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define EXYNOS_4x12_URSTCON_OTG_PHYLINK		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define EXYNOS_4x12_URSTCON_HOST_PHY		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* The following bit defines are presented in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * order taken from the Exynos4412 reference manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * During experiments with the hardware and debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * it was determined that the hardware behaves contrary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * to the manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * The following bit values were chaned accordingly to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * results of real hardware experiments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define EXYNOS_4x12_URSTCON_PHY1		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define EXYNOS_4x12_URSTCON_HSIC0		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define EXYNOS_4x12_URSTCON_HSIC1		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define EXYNOS_4x12_URSTCON_HOST_LINK_ALL	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define EXYNOS_4x12_URSTCON_HOST_LINK_P0	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define EXYNOS_4x12_URSTCON_HOST_LINK_P1	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define EXYNOS_4x12_URSTCON_HOST_LINK_P2	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Isolation, configured in the power management unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define EXYNOS_4x12_USB_ISOL_OFFSET		0x704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EXYNOS_4x12_USB_ISOL_OTG		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET	0x708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EXYNOS_4x12_USB_ISOL_HSIC0		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET	0x70c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define EXYNOS_4x12_USB_ISOL_HSIC1		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Mode switching SUB Device <-> Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EXYNOS_4x12_MODE_SWITCH_OFFSET		0x21c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define EXYNOS_4x12_MODE_SWITCH_MASK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EXYNOS_4x12_MODE_SWITCH_DEVICE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EXYNOS_4x12_MODE_SWITCH_HOST		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum exynos4x12_phy_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	EXYNOS4x12_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	EXYNOS4x12_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	EXYNOS4x12_HSIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	EXYNOS4x12_HSIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	EXYNOS4x12_NUM_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * exynos4x12_rate_to_clk() converts the supplied clock rate to the value that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * can be written to the phy register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int exynos4x12_rate_to_clk(unsigned long rate, u32 *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	case 9600 * KHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	case 10 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	case 12 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	case 19200 * KHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	case 20 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	case 24 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	case 50 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void exynos4x12_isol(struct samsung_usb2_phy_instance *inst, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	switch (inst->cfg->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	case EXYNOS4x12_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	case EXYNOS4x12_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		offset = EXYNOS_4x12_USB_ISOL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		mask = EXYNOS_4x12_USB_ISOL_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case EXYNOS4x12_HSIC0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		offset = EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		mask = EXYNOS_4x12_USB_ISOL_HSIC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	case EXYNOS4x12_HSIC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		offset = EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		mask = EXYNOS_4x12_USB_ISOL_HSIC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void exynos4x12_setup_clk(struct samsung_usb2_phy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	u32 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	clk = readl(drv->reg_phy + EXYNOS_4x12_UPHYCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	clk &= ~EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (drv->cfg->has_refclk_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		clk = EXYNOS_3250_UPHYCLK_REFCLKSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	clk |= drv->ref_reg_val << EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	clk |= EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	writel(clk, drv->reg_phy + EXYNOS_4x12_UPHYCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void exynos4x12_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	u32 rstbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	u32 phypwr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	u32 rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u32 pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	switch (inst->cfg->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case EXYNOS4x12_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		phypwr =	EXYNOS_4x12_UPHYPWR_PHY0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		rstbits =	EXYNOS_4x12_URSTCON_PHY0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case EXYNOS4x12_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		phypwr =	EXYNOS_4x12_UPHYPWR_PHY1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		rstbits =	EXYNOS_4x12_URSTCON_HOST_PHY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				EXYNOS_4x12_URSTCON_PHY1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				EXYNOS_4x12_URSTCON_HOST_LINK_P0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	case EXYNOS4x12_HSIC0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		phypwr =	EXYNOS_4x12_UPHYPWR_HSIC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		rstbits =	EXYNOS_4x12_URSTCON_HSIC0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				EXYNOS_4x12_URSTCON_HOST_LINK_P1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case EXYNOS4x12_HSIC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		phypwr =	EXYNOS_4x12_UPHYPWR_HSIC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		rstbits =	EXYNOS_4x12_URSTCON_HSIC1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 				EXYNOS_4x12_URSTCON_HOST_LINK_P1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		pwr &= ~phypwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		rst = readl(drv->reg_phy + EXYNOS_4x12_UPHYRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		rst |= rstbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		rst &= ~rstbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		/* The following delay is necessary for the reset sequence to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		 * completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		udelay(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		pwr |= phypwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void exynos4x12_power_on_int(struct samsung_usb2_phy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (inst->int_cnt++ > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	exynos4x12_setup_clk(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	exynos4x12_isol(inst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	exynos4x12_phy_pwr(inst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int exynos4x12_power_on(struct samsung_usb2_phy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (inst->ext_cnt++ > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (inst->cfg->id == EXYNOS4x12_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 						EXYNOS_4x12_MODE_SWITCH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 						EXYNOS_4x12_MODE_SWITCH_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 						EXYNOS_4x12_MODE_SWITCH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 						EXYNOS_4x12_MODE_SWITCH_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (inst->cfg->id == EXYNOS4x12_HSIC0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		inst->cfg->id == EXYNOS4x12_HSIC1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_HOST]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	exynos4x12_power_on_int(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void exynos4x12_power_off_int(struct samsung_usb2_phy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (inst->int_cnt-- > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	exynos4x12_isol(inst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	exynos4x12_phy_pwr(inst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int exynos4x12_power_off(struct samsung_usb2_phy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (inst->ext_cnt-- > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 						EXYNOS_4x12_MODE_SWITCH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 						EXYNOS_4x12_MODE_SWITCH_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (inst->cfg->id == EXYNOS4x12_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (inst->cfg->id == EXYNOS4x12_HSIC0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		inst->cfg->id == EXYNOS4x12_HSIC1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_HOST]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	exynos4x12_power_off_int(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct samsung_usb2_common_phy exynos4x12_phys[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.label		= "device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.id		= EXYNOS4x12_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.power_on	= exynos4x12_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.power_off	= exynos4x12_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.label		= "host",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.id		= EXYNOS4x12_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.power_on	= exynos4x12_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.power_off	= exynos4x12_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.label		= "hsic0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.id		= EXYNOS4x12_HSIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.power_on	= exynos4x12_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.power_off	= exynos4x12_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.label		= "hsic1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.id		= EXYNOS4x12_HSIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.power_on	= exynos4x12_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.power_off	= exynos4x12_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) const struct samsung_usb2_phy_config exynos3250_usb2_phy_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	.has_refclk_sel		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	.num_phys		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.phys			= exynos4x12_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.rate_to_clk		= exynos4x12_rate_to_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) const struct samsung_usb2_phy_config exynos4x12_usb2_phy_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.has_mode_switch	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.num_phys		= EXYNOS4x12_NUM_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.phys			= exynos4x12_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	.rate_to_clk		= exynos4x12_rate_to_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };