^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Kamil Debski <k.debski@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "phy-samsung-usb2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Exynos USB PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* PHY power control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EXYNOS_4210_UPHYPWR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EXYNOS_4210_UPHYPWR_PHY0_SUSPEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EXYNOS_4210_UPHYPWR_PHY0_PWR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EXYNOS_4210_UPHYPWR_PHY0_SLEEP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EXYNOS_4210_UPHYPWR_PHY0 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) EXYNOS_4210_UPHYPWR_PHY0_SUSPEND | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) EXYNOS_4210_UPHYPWR_PHY0_PWR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) EXYNOS_4210_UPHYPWR_PHY0_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EXYNOS_4210_UPHYPWR_PHY1_SUSPEND BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EXYNOS_4210_UPHYPWR_PHY1_PWR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EXYNOS_4210_UPHYPWR_PHY1_SLEEP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EXYNOS_4210_UPHYPWR_PHY1 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) EXYNOS_4210_UPHYPWR_PHY1_SUSPEND | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) EXYNOS_4210_UPHYPWR_PHY1_PWR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) EXYNOS_4210_UPHYPWR_PHY1_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EXYNOS_4210_UPHYPWR_HSIC0_SLEEP BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EXYNOS_4210_UPHYPWR_HSIC0 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) EXYNOS_4210_UPHYPWR_HSIC0_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EXYNOS_4210_UPHYPWR_HSIC1_SLEEP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EXYNOS_4210_UPHYPWR_HSIC1 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) EXYNOS_4210_UPHYPWR_HSIC1_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* PHY clock control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EXYNOS_4210_UPHYCLK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EXYNOS_4210_UPHYCLK_PHYFSEL_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EXYNOS_4210_UPHYCLK_PHY0_COMMON_ON BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EXYNOS_4210_UPHYCLK_PHY1_COMMON_ON BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* PHY reset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EXYNOS_4210_UPHYRST 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EXYNOS_4210_URSTCON_PHY0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EXYNOS_4210_URSTCON_OTG_HLINK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EXYNOS_4210_URSTCON_OTG_PHYLINK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EXYNOS_4210_URSTCON_PHY1_ALL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EXYNOS_4210_URSTCON_PHY1_P0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EXYNOS_4210_URSTCON_PHY1_P1P2 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EXYNOS_4210_URSTCON_HOST_LINK_ALL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EXYNOS_4210_URSTCON_HOST_LINK_P0 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EXYNOS_4210_URSTCON_HOST_LINK_P1 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EXYNOS_4210_URSTCON_HOST_LINK_P2 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Isolation, configured in the power management unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EXYNOS_4210_USB_ISOL_DEVICE_OFFSET 0x704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EXYNOS_4210_USB_ISOL_DEVICE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EXYNOS_4210_USB_ISOL_HOST_OFFSET 0x708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define EXYNOS_4210_USB_ISOL_HOST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* USBYPHY1 Floating prevention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define EXYNOS_4210_UPHY1CON 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define EXYNOS_4210_UPHY1CON_FLOAT_PREVENTION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Mode switching SUB Device <-> Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define EXYNOS_4210_MODE_SWITCH_OFFSET 0x21c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EXYNOS_4210_MODE_SWITCH_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define EXYNOS_4210_MODE_SWITCH_DEVICE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EXYNOS_4210_MODE_SWITCH_HOST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum exynos4210_phy_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) EXYNOS4210_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) EXYNOS4210_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) EXYNOS4210_HSIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) EXYNOS4210_HSIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) EXYNOS4210_NUM_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * exynos4210_rate_to_clk() converts the supplied clock rate to the value that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * can be written to the phy register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case 12 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case 24 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case 48 * MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void exynos4210_isol(struct samsung_usb2_phy_instance *inst, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) switch (inst->cfg->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case EXYNOS4210_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) offset = EXYNOS_4210_USB_ISOL_DEVICE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mask = EXYNOS_4210_USB_ISOL_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case EXYNOS4210_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) offset = EXYNOS_4210_USB_ISOL_HOST_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mask = EXYNOS_4210_USB_ISOL_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void exynos4210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct samsung_usb2_phy_driver *drv = inst->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 rstbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 phypwr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) switch (inst->cfg->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case EXYNOS4210_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) phypwr = EXYNOS_4210_UPHYPWR_PHY0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rstbits = EXYNOS_4210_URSTCON_PHY0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case EXYNOS4210_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) phypwr = EXYNOS_4210_UPHYPWR_PHY1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rstbits = EXYNOS_4210_URSTCON_PHY1_ALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) EXYNOS_4210_URSTCON_PHY1_P0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) EXYNOS_4210_URSTCON_PHY1_P1P2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) EXYNOS_4210_URSTCON_HOST_LINK_ALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) EXYNOS_4210_URSTCON_HOST_LINK_P0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writel(on, drv->reg_phy + EXYNOS_4210_UPHY1CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case EXYNOS4210_HSIC0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) phypwr = EXYNOS_4210_UPHYPWR_HSIC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) rstbits = EXYNOS_4210_URSTCON_PHY1_P1P2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) EXYNOS_4210_URSTCON_HOST_LINK_P1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case EXYNOS4210_HSIC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) phypwr = EXYNOS_4210_UPHYPWR_HSIC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rstbits = EXYNOS_4210_URSTCON_PHY1_P1P2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) EXYNOS_4210_URSTCON_HOST_LINK_P2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clk = readl(drv->reg_phy + EXYNOS_4210_UPHYCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) clk &= ~EXYNOS_4210_UPHYCLK_PHYFSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) clk |= drv->ref_reg_val << EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(clk, drv->reg_phy + EXYNOS_4210_UPHYCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pwr &= ~phypwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) rst = readl(drv->reg_phy + EXYNOS_4210_UPHYRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) rst |= rstbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) rst &= ~rstbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* The following delay is necessary for the reset sequence to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) udelay(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pwr |= phypwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int exynos4210_power_on(struct samsung_usb2_phy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Order of initialisation is important - first power then isolation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) exynos4210_phy_pwr(inst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) exynos4210_isol(inst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int exynos4210_power_off(struct samsung_usb2_phy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) exynos4210_isol(inst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) exynos4210_phy_pwr(inst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct samsung_usb2_common_phy exynos4210_phys[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .label = "device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .id = EXYNOS4210_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .power_on = exynos4210_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .power_off = exynos4210_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .label = "host",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .id = EXYNOS4210_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .power_on = exynos4210_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .power_off = exynos4210_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .label = "hsic0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .id = EXYNOS4210_HSIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .power_on = exynos4210_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .power_off = exynos4210_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .label = "hsic1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .id = EXYNOS4210_HSIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .power_on = exynos4210_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .power_off = exynos4210_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) const struct samsung_usb2_phy_config exynos4210_usb2_phy_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .has_mode_switch = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .num_phys = EXYNOS4210_NUM_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .phys = exynos4210_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .rate_to_clk = exynos4210_rate_to_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags