^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Samsung Exynos SoC series PCIe PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Phy provider for PCIe controller on Exynos SoC series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2017 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Jaehoon Chung <jh80.chung@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* PCIe Purple registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCIE_PHY_GLOBAL_RESET 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCIE_PHY_COMMON_RESET 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCIE_PHY_CMN_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCIE_PHY_MAC_RESET 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCIE_PHY_PLL_LOCKED 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCIE_PHY_TRSVREG_RESET 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCIE_PHY_TRSV_RESET 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* PCIe PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCIE_PHY_IMPEDANCE 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCIE_PHY_PLL_DIV_0 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCIE_PHY_PLL_BIAS 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCIE_PHY_DCC_FEEDBACK 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCIE_PHY_PLL_DIV_1 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCIE_PHY_COMMON_POWER 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCIE_PHY_COMMON_PD_CMN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCIE_PHY_TRSV0_EMP_LVL 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCIE_PHY_TRSV0_DRV_LVL 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCIE_PHY_TRSV0_RXCDR 0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCIE_PHY_TRSV0_POWER 0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCIE_PHY_TRSV0_PD_TSV BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCIE_PHY_TRSV0_LVCC 0x0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCIE_PHY_TRSV1_EMP_LVL 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCIE_PHY_TRSV1_RXCDR 0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCIE_PHY_TRSV1_POWER 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCIE_PHY_TRSV1_PD_TSV BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCIE_PHY_TRSV1_LVCC 0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCIE_PHY_TRSV2_EMP_LVL 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCIE_PHY_TRSV2_RXCDR 0x22c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCIE_PHY_TRSV2_POWER 0x244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCIE_PHY_TRSV2_PD_TSV BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCIE_PHY_TRSV2_LVCC 0x25c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCIE_PHY_TRSV3_RXCDR 0x2ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCIE_PHY_TRSV3_POWER 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCIE_PHY_TRSV3_PD_TSV BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCIE_PHY_TRSV3_LVCC 0x31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct exynos_pcie_phy_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) const struct phy_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* For Exynos pcie phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct exynos_pcie_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const struct exynos_pcie_phy_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *blk_base; /* For exynos5440 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writel(val, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return readl(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* For Exynos5440 specific functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int exynos5440_pcie_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* DCC feedback control off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* set TX/RX impedance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* set 50Mhz PHY clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* set TX Differential output for lane 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* set TX Pre-emphasis Level Control for lane 0 to minimum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* set RX clock and data recovery bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* change TX Pre-emphasis Level Control for lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* set LVCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* pulse for common reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int exynos5440_pcie_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val &= ~PCIE_PHY_COMMON_PD_CMN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) val &= ~PCIE_PHY_TRSV0_PD_TSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) val &= ~PCIE_PHY_TRSV1_PD_TSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) val &= ~PCIE_PHY_TRSV2_PD_TSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val &= ~PCIE_PHY_TRSV3_PD_TSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int exynos5440_pcie_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) (val != 0), 1, 500)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) val |= PCIE_PHY_COMMON_PD_CMN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val |= PCIE_PHY_TRSV0_PD_TSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val |= PCIE_PHY_TRSV1_PD_TSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val |= PCIE_PHY_TRSV2_PD_TSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val |= PCIE_PHY_TRSV3_PD_TSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int exynos5440_pcie_phy_reset(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct phy_ops exynos5440_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .init = exynos5440_pcie_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .power_on = exynos5440_pcie_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .power_off = exynos5440_pcie_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .reset = exynos5440_pcie_phy_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .ops = &exynos5440_phy_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct of_device_id exynos_pcie_phy_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .compatible = "samsung,exynos5440-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .data = &exynos5440_pcie_phy_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int exynos_pcie_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct exynos_pcie_phy *exynos_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) const struct exynos_pcie_phy_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) drv_data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!exynos_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) exynos_phy->phy_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (IS_ERR(exynos_phy->phy_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return PTR_ERR(exynos_phy->phy_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) exynos_phy->blk_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (IS_ERR(exynos_phy->blk_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return PTR_ERR(exynos_phy->blk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) exynos_phy->drv_data = drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (IS_ERR(generic_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return PTR_ERR(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) phy_set_drvdata(generic_phy, exynos_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct platform_driver exynos_pcie_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .probe = exynos_pcie_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .of_match_table = exynos_pcie_phy_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .name = "exynos_pcie_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) builtin_platform_driver(exynos_pcie_phy_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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