^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013,2016 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/soc/samsung/exynos-regs-pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum exynos_mipi_phy_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) EXYNOS_MIPI_PHY_ID_NONE = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) EXYNOS_MIPI_PHY_ID_CSIS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) EXYNOS_MIPI_PHY_ID_DSIM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) EXYNOS_MIPI_PHY_ID_CSIS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) EXYNOS_MIPI_PHY_ID_DSIM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) EXYNOS_MIPI_PHY_ID_CSIS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) EXYNOS_MIPI_PHYS_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum exynos_mipi_phy_regmap_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) EXYNOS_MIPI_REGMAP_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) EXYNOS_MIPI_REGMAP_CAM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) EXYNOS_MIPI_REGMAP_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) EXYNOS_MIPI_REGMAPS_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct mipi_phy_device_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int num_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int num_regmaps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const char *regmap_names[EXYNOS_MIPI_REGMAPS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct exynos_mipi_phy_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum exynos_mipi_phy_id coupled_phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 enable_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum exynos_mipi_phy_regmap_id enable_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 resetn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int resetn_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum exynos_mipi_phy_regmap_id resetn_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } phys[EXYNOS_MIPI_PHYS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .num_regmaps = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .regmap_names = {"syscon"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .num_phys = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .phys = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* EXYNOS_MIPI_PHY_ID_CSIS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* EXYNOS_MIPI_PHY_ID_DSIM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* EXYNOS_MIPI_PHY_ID_CSIS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* EXYNOS_MIPI_PHY_ID_DSIM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .num_regmaps = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .regmap_names = {"syscon"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .num_phys = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .phys = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* EXYNOS_MIPI_PHY_ID_CSIS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* EXYNOS_MIPI_PHY_ID_DSIM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* EXYNOS_MIPI_PHY_ID_CSIS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* EXYNOS_MIPI_PHY_ID_DSIM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* EXYNOS_MIPI_PHY_ID_CSIS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define EXYNOS5433_SYSREG_DISP_MIPI_PHY 0x100C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON 0x1014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON 0x1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .num_regmaps = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .regmap_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "samsung,pmu-syscon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "samsung,disp-sysreg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "samsung,cam0-sysreg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "samsung,cam1-sysreg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .num_phys = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .phys = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* EXYNOS_MIPI_PHY_ID_CSIS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .resetn_val = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* EXYNOS_MIPI_PHY_ID_DSIM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .resetn_val = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* EXYNOS_MIPI_PHY_ID_CSIS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .resetn_val = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* EXYNOS_MIPI_PHY_ID_DSIM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .resetn_val = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* EXYNOS_MIPI_PHY_ID_CSIS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .enable_val = EXYNOS4_PHY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .enable_map = EXYNOS_MIPI_REGMAP_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .resetn_val = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct exynos_mipi_video_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int num_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct video_phy_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const struct exynos_mipi_phy_desc *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) } phys[EXYNOS_MIPI_PHYS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct exynos_mipi_video_phy *state, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct regmap *enable_map = state->regmaps[data->enable_map];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct regmap *resetn_map = state->regmaps[data->resetn_map];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spin_lock(&state->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* disable in PMU sysreg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!on && data->coupled_phy_id >= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) state->phys[data->coupled_phy_id].phy->power_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) regmap_update_bits(enable_map, data->enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) data->enable_val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) regmap_update_bits(resetn_map, data->resetn_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) data->resetn_val, data->resetn_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) regmap_update_bits(resetn_map, data->resetn_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) data->resetn_val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* enable in PMU sysreg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) regmap_update_bits(enable_map, data->enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) data->enable_val, data->enable_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) spin_unlock(&state->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define to_mipi_video_phy(desc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int exynos_mipi_video_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return __set_phy_state(phy_desc->data, state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int exynos_mipi_video_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return __set_phy_state(phy_desc->data, state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (WARN_ON(args->args[0] >= state->num_phys))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return state->phys[args->args[0]].phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct phy_ops exynos_mipi_video_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .power_on = exynos_mipi_video_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .power_off = exynos_mipi_video_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) const struct mipi_phy_device_desc *phy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct exynos_mipi_video_phy *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) phy_dev = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!phy_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) for (i = 0; i < phy_dev->num_regmaps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) state->regmaps[i] = syscon_regmap_lookup_by_phandle(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) phy_dev->regmap_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (IS_ERR(state->regmaps[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return PTR_ERR(state->regmaps[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) state->num_phys = phy_dev->num_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) spin_lock_init(&state->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_set_drvdata(dev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) for (i = 0; i < state->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct phy *phy = devm_phy_create(dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) &exynos_mipi_video_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_err(dev, "failed to create PHY %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) state->phys[i].phy = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) state->phys[i].index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) state->phys[i].data = &phy_dev->phys[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) phy_set_drvdata(phy, &state->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) phy_provider = devm_of_phy_provider_register(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) exynos_mipi_video_phy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .compatible = "samsung,s5pv210-mipi-video-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .data = &s5pv210_mipi_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .compatible = "samsung,exynos5420-mipi-video-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .data = &exynos5420_mipi_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .compatible = "samsung,exynos5433-mipi-video-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .data = &exynos5433_mipi_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct platform_driver exynos_mipi_video_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .probe = exynos_mipi_video_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .of_match_table = exynos_mipi_video_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .name = "exynos-mipi-video-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) module_platform_driver(exynos_mipi_video_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_DESCRIPTION("Samsung S5P/Exynos SoC MIPI CSI-2/DSI PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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