^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Samsung Exynos SoC series Display Port PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Jingoo Han <jg1.han@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/soc/samsung/exynos-regs-pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct exynos_dp_video_phy_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 phy_ctrl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct exynos_dp_video_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct regmap *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) const struct exynos_dp_video_phy_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int exynos_dp_video_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct exynos_dp_video_phy *state = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Disable power isolation on DP-PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) EXYNOS4_PHY_ENABLE, EXYNOS4_PHY_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int exynos_dp_video_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct exynos_dp_video_phy *state = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Enable power isolation on DP-PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) EXYNOS4_PHY_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct phy_ops exynos_dp_video_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .power_on = exynos_dp_video_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .power_off = exynos_dp_video_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct exynos_dp_video_phy_drvdata exynos5250_dp_video_phy = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .phy_ctrl_offset = EXYNOS5_DPTX_PHY_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct exynos_dp_video_phy_drvdata exynos5420_dp_video_phy = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .phy_ctrl_offset = EXYNOS5420_DPTX_PHY_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct of_device_id exynos_dp_video_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .compatible = "samsung,exynos5250-dp-video-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .data = &exynos5250_dp_video_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .compatible = "samsung,exynos5420-dp-video-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .data = &exynos5420_dp_video_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MODULE_DEVICE_TABLE(of, exynos_dp_video_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int exynos_dp_video_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct exynos_dp_video_phy *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) state->regs = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "samsung,pmu-syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (IS_ERR(state->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_err(dev, "Failed to lookup PMU regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return PTR_ERR(state->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) state->drvdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) phy = devm_phy_create(dev, NULL, &exynos_dp_video_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_err(dev, "failed to create Display Port PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) phy_set_drvdata(phy, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct platform_driver exynos_dp_video_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .probe = exynos_dp_video_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "exynos-dp-video-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .of_match_table = exynos_dp_video_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) module_platform_driver(exynos_dp_video_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MODULE_DESCRIPTION("Samsung Exynos SoC DP PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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