^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip USBDP Combo PHY with Samsung IP block driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2021 Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/usb/typec_dp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/usb/typec_mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/phy/phy-rockchip-usbdp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BIT_WRITEABLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DP_BW_RBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DP_BW_HBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DP_BW_HBR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DP_BW_HBR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) UDPHY_MODE_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) UDPHY_MODE_USB = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) UDPHY_MODE_DP = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct udphy_grf_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int bitend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int bitstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct udphy_grf_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* u2phy-grf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct udphy_grf_reg bvalid_phy_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct udphy_grf_reg bvalid_grf_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* usb-grf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct udphy_grf_reg usb3otg0_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct udphy_grf_reg usb3otg1_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* usbdpphy-grf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct udphy_grf_reg low_pwrn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct udphy_grf_reg rx_lfps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct udphy_vogrf_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* vo-grf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct udphy_grf_reg hpd_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct dp_tx_drv_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 trsv_reg0204;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 trsv_reg0205;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 trsv_reg0206;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 trsv_reg0207;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct rockchip_udphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct rockchip_udphy_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* resets to be requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const char * const *rst_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int num_rsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct udphy_grf_cfg grfcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct udphy_vogrf_cfg vogrfcfg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int (*combophy_init)(struct rockchip_udphy *udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int (*dp_phy_set_rate)(struct rockchip_udphy *udphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct phy_configure_opts_dp *dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int (*dp_phy_set_voltages)(struct rockchip_udphy *udphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct phy_configure_opts_dp *dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int (*hpd_event_trigger)(struct rockchip_udphy *udphy, bool hpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int (*dplane_enable)(struct rockchip_udphy *udphy, int dp_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int (*dplane_select)(struct rockchip_udphy *udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct rockchip_udphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct regmap *pma_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct regmap *u2phygrf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct regmap *udphygrf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct regmap *usbgrf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct regmap *vogrf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct typec_switch *sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct typec_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct mutex mutex; /* mutex to protect access to individual PHYs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* clocks and rests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk *refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct reset_control **rsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* PHY status management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) bool flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bool mode_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* utilized for USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) bool hs; /* flag for high-speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* utilized for DP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct gpio_desc *sbu1_dc_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct gpio_desc *sbu2_dc_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 lane_mux_sel[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 dp_lane_sel[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 dp_aux_dout_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 dp_aux_din_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool dp_sink_hpd_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool dp_sink_hpd_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* PHY const config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const struct rockchip_udphy_cfg *cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* voltage swing 0, pre-emphasis 0->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { 0x20, 0x10, 0x42, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 0x26, 0x14, 0x42, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 0x29, 0x18, 0x42, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { 0x2b, 0x1c, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* voltage swing 1, pre-emphasis 0->2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 0x23, 0x10, 0x42, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 0x2a, 0x17, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 0x2b, 0x1a, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* voltage swing 2, pre-emphasis 0->1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0x27, 0x10, 0x42, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 0x2b, 0x17, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* voltage swing 3, pre-emphasis 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0x29, 0x10, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* voltage swing 0, pre-emphasis 0->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 0x20, 0x10, 0x42, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 0x26, 0x14, 0x42, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 0x29, 0x18, 0x42, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 0x2b, 0x1c, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* voltage swing 1, pre-emphasis 0->2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 0x23, 0x10, 0x42, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 0x2a, 0x17, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0x2b, 0x1a, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* voltage swing 2, pre-emphasis 0->1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 0x27, 0x10, 0x43, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 0x2b, 0x17, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* voltage swing 3, pre-emphasis 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 0x29, 0x10, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* voltage swing 0, pre-emphasis 0->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 0x21, 0x10, 0x42, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 0x26, 0x14, 0x42, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 0x26, 0x16, 0x43, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 0x2a, 0x19, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* voltage swing 1, pre-emphasis 0->2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { 0x24, 0x10, 0x42, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { 0x2a, 0x17, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 0x2b, 0x1a, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* voltage swing 2, pre-emphasis 0->1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 0x28, 0x10, 0x42, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 0x2b, 0x17, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* voltage swing 3, pre-emphasis 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 0x28, 0x10, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* voltage swing 0, pre-emphasis 0->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 0x21, 0x10, 0x42, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 0x26, 0x14, 0x42, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0x26, 0x16, 0x43, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0x29, 0x18, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* voltage swing 1, pre-emphasis 0->2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0x24, 0x10, 0x42, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 0x2a, 0x18, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 0x2b, 0x1b, 0x43, 0xe7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* voltage swing 2, pre-emphasis 0->1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 0x27, 0x10, 0x42, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 0x2b, 0x18, 0x43, 0xe7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* voltage swing 3, pre-emphasis 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 0x28, 0x10, 0x43, 0xe7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x0090, 0x68}, {0x0094, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x0128, 0x24}, {0x012c, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x0130, 0x3f}, {0x0134, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x015c, 0xa9}, {0x0160, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x0164, 0x71}, {0x0168, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x0174, 0xa9}, {0x0178, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x017c, 0x71}, {0x0180, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x018c, 0x41}, {0x0190, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x0194, 0x05}, {0x01ac, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x01b0, 0x17}, {0x01b4, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x01b8, 0x2a}, {0x01c8, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x01cc, 0x08}, {0x01d0, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x01d4, 0x04}, {0x01d8, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x01dc, 0x01}, {0x01e0, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x01e4, 0x03}, {0x01f0, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x01f4, 0x02}, {0x01f8, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x01fc, 0x29}, {0x0208, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x020c, 0x17}, {0x0210, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x0214, 0x2a}, {0x0224, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x03f0, 0x0a}, {0x03f4, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x03f8, 0x07}, {0x03fc, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x0404, 0x12}, {0x0408, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x040c, 0x1a}, {0x0410, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x0ce0, 0x68}, {0x0ce8, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x0cf0, 0x87}, {0x0cf8, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x0d00, 0x70}, {0x0d08, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x1ce0, 0x68}, {0x1ce8, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x1cf0, 0x87}, {0x1cf8, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x1d00, 0x70}, {0x1d08, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x0a3c, 0xd0}, {0x0a44, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x0a48, 0x01}, {0x0a4c, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x0a54, 0xe0}, {0x0a5c, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x0a64, 0xa8}, {0x1a3c, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x1a44, 0xd0}, {0x1a48, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x1a4c, 0x0d}, {0x1a54, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x1a5c, 0xe0}, {0x1a64, 0xa8}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct reg_sequence rk3588_udphy_26m_refclk_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x0830, 0x07}, {0x085c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x1030, 0x07}, {0x105c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x1830, 0x07}, {0x185c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x2030, 0x07}, {0x205c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x0228, 0x38}, {0x0104, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x0248, 0x44}, {0x038C, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x0878, 0x04}, {0x1878, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x0898, 0x77}, {0x1898, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x0054, 0x01}, {0x00e0, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x0060, 0x24}, {0x0064, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x0070, 0x76}, {0x0234, 0xE8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x0AF4, 0x15}, {0x1AF4, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x081C, 0xE5}, {0x181C, 0xE5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x099C, 0x48}, {0x199C, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x09A4, 0x07}, {0x09A8, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x19A4, 0x07}, {0x19A8, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x09B8, 0x3E}, {0x19B8, 0x3E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x09E4, 0x02}, {0x19E4, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x0A34, 0x1E}, {0x1A34, 0x1E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x0A98, 0x2F}, {0x1A98, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x0c30, 0x0E}, {0x0C48, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x1C30, 0x0E}, {0x1C48, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x028C, 0x18}, {0x0AF0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x1AF0, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct reg_sequence rk3588_udphy_init_sequence[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x0104, 0x44}, {0x0234, 0xE8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x0248, 0x44}, {0x028C, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x081C, 0xE5}, {0x0878, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x0994, 0x1C}, {0x0AF0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x181C, 0xE5}, {0x1878, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x1994, 0x1C}, {0x1AF0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x0428, 0x60}, {0x0D58, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x1D58, 0x33}, {0x0990, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x0D64, 0x17}, {0x08C8, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x1990, 0x74}, {0x1D64, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x18C8, 0x13}, {0x0D90, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x0DA8, 0x40}, {0x0DC0, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x0DD8, 0x40}, {0x1D90, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x1DA8, 0x40}, {0x1DC0, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x1DD8, 0x40}, {0x03C0, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x03C4, 0x06}, {0x0E10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x1E10, 0x00}, {0x043C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x0D2C, 0xFF}, {0x1D2C, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x0D34, 0x0F}, {0x1D34, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x08FC, 0x2A}, {0x0914, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x0A30, 0x03}, {0x0E38, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x0ECC, 0x27}, {0x0ED0, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x0ED4, 0x26}, {0x18FC, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x1914, 0x28}, {0x1A30, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x1E38, 0x05}, {0x1ECC, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x1ED0, 0x22}, {0x1ED4, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x0048, 0x0F}, {0x0060, 0x3C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x0064, 0xF7}, {0x006C, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x0070, 0x7D}, {0x0074, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x0AF4, 0x1A}, {0x1AF4, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x0440, 0x3F}, {0x10D4, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x20D4, 0x08}, {0x00D4, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x0024, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static inline int grfreg_write(struct regmap *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) const struct udphy_grf_reg *reg, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 val, mask, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) tmp = en ? reg->enable : reg->disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mask = GENMASK(reg->bitend, reg->bitstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return regmap_write(base, reg->offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int udphy_clk_init(struct rockchip_udphy *udphy, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (udphy->num_clks < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* used for configure phy reference clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) for (i = 0; i < udphy->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!strncmp(udphy->clks[i].id, "refclk", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) udphy->refclk = udphy->clks[i].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!udphy->refclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_warn(udphy->dev, "no refclk found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int udphy_reset_init(struct rockchip_udphy *udphy, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) sizeof(*udphy->rsts), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!udphy->rsts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (idx = 0; idx < cfg->num_rsts; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) const char *name = cfg->rst_list[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rst = devm_reset_control_get(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(dev, "failed to get %s reset\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) devm_kfree(dev, (void *)udphy->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return PTR_ERR(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) udphy->rsts[idx] = rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int udphy_get_rst_idx(const char * const *list, int num, char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) for (idx = 0; idx < num; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!strcmp(list[idx], name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return reset_control_assert(udphy->rsts[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return reset_control_deassert(udphy->rsts[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) const struct udphy_grf_reg *preg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) grfreg_write(udphy->usbgrf, preg, disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * C/E(Normal) dpln3 dpln2 dpln0 dpln1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * C/E(Flip ) dpln0 dpln1 dpln3 dpln2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * D/F(Normal) usbrx usbtx dpln0 dpln1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * D/F(Flip ) dpln0 dpln1 usbrx usbtx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * A(Normal ) dpln3 dpln1 dpln2 dpln0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * A(Flip ) dpln2 dpln0 dpln3 dpln1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * B(Normal ) usbrx usbtx dpln1 dpln0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * B(Flip ) dpln1 dpln0 usbrx usbtx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * 2 Mapping the lanes in dtsi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * sample as follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * B11-B10 A2-A3 A11-A10 B2-B3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * <0 1 2 3> dpln0 dpln1 dpln2 dpln3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * <2 3 0 1> dpln2 dpln3 dpln0 dpln1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * sample as follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * B11-B10 A2-A3 A11-A10 B2-B3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * <0 1> dpln0 dpln1 usbrx usbtx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * <2 3> usbrx usbtx dpln0 dpln1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int udphy_dplane_select(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (cfg->dplane_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return cfg->dplane_select(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int udphy_dplane_get(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int dp_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) switch (udphy->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case UDPHY_MODE_DP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dp_lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case UDPHY_MODE_DP_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dp_lanes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case UDPHY_MODE_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dp_lanes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return dp_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (cfg->dplane_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = cfg->dplane_enable(udphy, dp_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (udphy->flip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) udphy->dp_lane_sel[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) udphy->dp_lane_sel[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) udphy->dp_lane_sel[2] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) udphy->dp_lane_sel[3] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) udphy->dp_lane_sel[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) udphy->dp_lane_sel[1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) udphy->dp_lane_sel[2] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) udphy->dp_lane_sel[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) udphy->mode = UDPHY_MODE_DP_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int udphy_orien_sw_set(struct typec_switch *sw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) enum typec_orientation orien)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct rockchip_udphy *udphy = typec_switch_get_drvdata(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mutex_lock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (orien == TYPEC_ORIENTATION_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* unattached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) udphy_usb_bvalid_enable(udphy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) goto unlock_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) upphy_set_typec_default_mapping(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) udphy_usb_bvalid_enable(udphy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unlock_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mutex_unlock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int udphy_setup_orien_switch(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct typec_switch_desc sw_desc = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sw_desc.drvdata = udphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) sw_desc.fwnode = dev_fwnode(udphy->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) sw_desc.set = udphy_orien_sw_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) udphy->sw = typec_switch_register(udphy->dev, &sw_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (IS_ERR(udphy->sw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_err(udphy->dev, "Error register typec orientation switch: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PTR_ERR(udphy->sw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return PTR_ERR(udphy->sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static void udphy_orien_switch_unregister(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct rockchip_udphy *udphy = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) typec_switch_unregister(udphy->sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int udphy_setup(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_err(udphy->dev, "failed to enable clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (cfg->combophy_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ret = cfg->combophy_init(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dev_err(udphy->dev, "failed to init combophy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int udphy_disable(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) for (i = 0; i < cfg->num_rsts; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) reset_control_assert(udphy->rsts[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) int ret, i, len, num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) udphy->mode = UDPHY_MODE_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) num_lanes = len / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (num_lanes != 2 && num_lanes != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(udphy->dev, "invalid number of lane mux\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = of_property_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dev_err(udphy->dev, "get dp lane mux failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) for (i = 0; i < num_lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (udphy->dp_lane_sel[i] > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) for (j = i + 1; j < num_lanes; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dev_err(udphy->dev, "set repeat lane mux value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) udphy->mode = UDPHY_MODE_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (num_lanes == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) udphy->mode |= UDPHY_MODE_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static int udphy_get_initial_status(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dev_err(udphy->dev, "failed to enable clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) for (i = 0; i < cfg->num_rsts; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) reset_control_deassert(udphy->rsts[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) udphy->status = UDPHY_MODE_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) udphy_disable(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static int udphy_parse_dt(struct rockchip_udphy *udphy, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) enum usb_device_speed maximum_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (IS_ERR(udphy->u2phygrf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_warn(dev, "missing u2phy-grf dt node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) udphy->u2phygrf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return PTR_ERR(udphy->u2phygrf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (IS_ERR(udphy->udphygrf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (PTR_ERR(udphy->udphygrf) == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev_warn(dev, "missing usbdpphy-grf dt node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) udphy->udphygrf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return PTR_ERR(udphy->udphygrf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (IS_ERR(udphy->usbgrf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (PTR_ERR(udphy->usbgrf) == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev_warn(dev, "missing usb-grf dt node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) udphy->usbgrf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return PTR_ERR(udphy->usbgrf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (IS_ERR(udphy->vogrf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (PTR_ERR(udphy->vogrf) == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev_warn(dev, "missing vo-grf dt node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) udphy->vogrf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return PTR_ERR(udphy->vogrf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = udphy_parse_lane_mux_data(udphy, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (IS_ERR(udphy->sbu1_dc_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return PTR_ERR(udphy->sbu1_dc_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (IS_ERR(udphy->sbu2_dc_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return PTR_ERR(udphy->sbu2_dc_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (device_property_present(dev, "maximum-speed")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) maximum_speed = usb_get_maximum_speed(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = udphy_clk_init(udphy, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = udphy_reset_init(udphy, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (!(udphy->mode & mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (udphy->status == UDPHY_MODE_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) udphy->mode_change = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = udphy_setup(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (udphy->mode & UDPHY_MODE_USB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) udphy_u3_port_disable(udphy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) } else if (udphy->mode_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) udphy->mode_change = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) udphy->status = UDPHY_MODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (udphy->mode == UDPHY_MODE_DP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) udphy_u3_port_disable(udphy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ret = udphy_disable(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = udphy_setup(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) udphy->status |= mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (!(udphy->mode & mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (!udphy->status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) udphy->status &= ~mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (udphy->status == UDPHY_MODE_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ret = udphy_disable(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static int rockchip_dp_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct rockchip_udphy *udphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) int ret, dp_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) mutex_lock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dp_lanes = udphy_dplane_get(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) phy_set_bus_width(phy, dp_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ret = udphy_power_on(udphy, UDPHY_MODE_DP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = udphy_dplane_enable(udphy, dp_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = udphy_dplane_select(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) mutex_unlock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * If data send by aux channel too fast after phy power on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * the aux may be not ready which will cause aux error. Adding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * delay to avoid this issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int rockchip_dp_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct rockchip_udphy *udphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) mutex_lock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ret = udphy_dplane_enable(udphy, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = udphy_power_off(udphy, UDPHY_MODE_DP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) mutex_unlock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static int rockchip_dp_phy_verify_link_rate(unsigned int link_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) switch (link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static int rockchip_dp_phy_verify_config(struct rockchip_udphy *udphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* If changing link rate was required, verify it's supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = rockchip_dp_phy_verify_link_rate(dp->link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Verify lane count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) switch (dp->lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* valid lane count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * If changing voltages is required, check swing and pre-emphasis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * levels, per-lane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (dp->set_voltages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* Lane count verified previously. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) for (i = 0; i < dp->lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (dp->voltage[i] > 3 || dp->pre[i] > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * Sum of voltage swing and pre-emphasis levels cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * exceed 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (dp->voltage[i] + dp->pre[i] > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int rockchip_dp_phy_configure(struct phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) union phy_configure_opts *opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct rockchip_udphy *udphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret = rockchip_dp_phy_verify_config(udphy, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (opts->dp.set_rate && cfg->dp_phy_set_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret = cfg->dp_phy_set_rate(udphy, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dev_err(udphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "rockchip_hdptx_phy_set_rate failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (opts->dp.set_voltages && cfg->dp_phy_set_voltages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = cfg->dp_phy_set_voltages(udphy, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dev_err(udphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) "rockchip_dp_phy_set_voltages failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const struct phy_ops rockchip_dp_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .power_on = rockchip_dp_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .power_off = rockchip_dp_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .configure = rockchip_dp_phy_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int rockchip_u3phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct rockchip_udphy *udphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) mutex_lock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* DP only or high-speed, disable U3 port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) udphy_u3_port_disable(udphy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ret = udphy_power_on(udphy, UDPHY_MODE_USB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) mutex_unlock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static int rockchip_u3phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct rockchip_udphy *udphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mutex_lock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* DP only or high-speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ret = udphy_power_off(udphy, UDPHY_MODE_USB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) mutex_unlock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static const struct phy_ops rockchip_u3phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .init = rockchip_u3phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .exit = rockchip_u3phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int usbdp_typec_mux_set(struct typec_mux *mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct typec_mux_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct rockchip_udphy *udphy = typec_mux_get_drvdata(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) mutex_lock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) switch (state->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) case TYPEC_DP_STATE_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) case TYPEC_DP_STATE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) mode = UDPHY_MODE_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case TYPEC_DP_STATE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (udphy->flip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) mode = UDPHY_MODE_DP_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct typec_displayport_data *data = state->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (cfg->hpd_event_trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) cfg->hpd_event_trigger(udphy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) } else if (data->status & DP_STATUS_IRQ_HPD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (cfg->hpd_event_trigger) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) cfg->hpd_event_trigger(udphy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) usleep_range(750, 800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) cfg->hpd_event_trigger(udphy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) } else if (data->status & DP_STATUS_HPD_STATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (udphy->mode != mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) udphy->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) udphy->mode_change = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (cfg->hpd_event_trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) cfg->hpd_event_trigger(udphy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (cfg->hpd_event_trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) cfg->hpd_event_trigger(udphy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) mutex_unlock(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static int udphy_setup_typec_mux(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct typec_mux_desc mux_desc = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) mux_desc.drvdata = udphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) mux_desc.fwnode = dev_fwnode(udphy->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) mux_desc.set = usbdp_typec_mux_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) udphy->mux = typec_mux_register(udphy->dev, &mux_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (IS_ERR(udphy->mux)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) dev_err(udphy->dev, "Error register typec mux: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PTR_ERR(udphy->mux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return PTR_ERR(udphy->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static void udphy_typec_mux_unregister(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct rockchip_udphy *udphy = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) typec_mux_unregister(udphy->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static u32 udphy_dp_get_max_link_rate(struct rockchip_udphy *udphy, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) u32 max_link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret = of_property_read_u32(np, "max-link-rate", &max_link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return 8100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = rockchip_dp_phy_verify_link_rate(max_link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) dev_warn(udphy->dev, "invalid max-link-rate value:%d\n", max_link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) max_link_rate = 8100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return max_link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static const struct regmap_config rockchip_udphy_pma_regmap_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .max_register = 0x20dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static int rockchip_udphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct device_node *child_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct rockchip_udphy *udphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) const struct rockchip_udphy_cfg *phy_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) int id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (!udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) id = of_alias_get_id(dev->of_node, "usbdp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) udphy->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) phy_cfgs = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (!phy_cfgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dev_err(dev, "no OF data can be matched with %p node\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) udphy->cfgs = phy_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) &rockchip_udphy_pma_regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (IS_ERR(udphy->pma_regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return PTR_ERR(udphy->pma_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ret = udphy_parse_dt(udphy, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = udphy_get_initial_status(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) mutex_init(&udphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) udphy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) platform_set_drvdata(pdev, udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (device_property_present(dev, "orientation-switch")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ret = udphy_setup_orien_switch(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ret = devm_add_action_or_reset(dev, udphy_orien_switch_unregister, udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (device_property_present(dev, "svid")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ret = udphy_setup_typec_mux(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret = devm_add_action_or_reset(dev, udphy_typec_mux_unregister, udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) for_each_available_child_of_node(np, child_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (of_node_name_eq(child_np, "dp-port")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) phy = devm_phy_create(dev, child_np, &rockchip_dp_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_err(dev, "failed to create dp phy: %pOFn\n", child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) phy_set_bus_width(phy, udphy_dplane_get(udphy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) phy->attrs.max_link_rate = udphy_dp_get_max_link_rate(udphy, child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) } else if (of_node_name_eq(child_np, "u3-port")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) phy = devm_phy_create(dev, child_np, &rockchip_u3phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) dev_err(dev, "failed to create usb phy: %pOFn\n", child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) phy_set_drvdata(phy, udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dev_err(dev, "failed to register phy provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) of_node_put(child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* configure phy reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) rate = clk_get_rate(udphy->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) dev_dbg(udphy->dev, "refclk freq %ld\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) case 24000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_24m_refclk_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /* register default is 26MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_26m_refclk_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) ARRAY_SIZE(rk3588_udphy_26m_refclk_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* LCPLL check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (udphy->mode & UDPHY_MODE_USB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (udphy->mode & UDPHY_MODE_USB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (!udphy->flip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret = regmap_read_poll_timeout(udphy->pma_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) 200, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret = regmap_read_poll_timeout(udphy->pma_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) 200, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static int rk3588_udphy_init(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /* enable rx lfps for usb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (udphy->mode & UDPHY_MODE_USB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* Step 1: power on pma and deassert apb rstn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) udphy_reset_deassert(udphy, "pma_apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) udphy_reset_deassert(udphy, "pcs_apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* Step 2: set init sequence and phy refclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_init_sequence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) ARRAY_SIZE(rk3588_udphy_init_sequence));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dev_err(udphy->dev, "init sequence set error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) goto assert_apb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ret = rk3588_udphy_refclk_set(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) dev_err(udphy->dev, "refclk set error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) goto assert_apb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* Step 3: configure lane mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /* Step 4: deassert init rstn and wait for 200ns from datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (udphy->mode & UDPHY_MODE_USB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) udphy_reset_deassert(udphy, "init");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (udphy->mode & UDPHY_MODE_DP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) CMN_DP_INIT_RSTN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /* Step 5: deassert cmn/lane rstn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (udphy->mode & UDPHY_MODE_USB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) udphy_reset_deassert(udphy, "cmn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) udphy_reset_deassert(udphy, "lane");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /* Step 6: wait for lock done of pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ret = rk3588_udphy_status_check(udphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) goto assert_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) assert_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) udphy_reset_assert(udphy, "init");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) udphy_reset_assert(udphy, "cmn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) udphy_reset_assert(udphy, "lane");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) assert_apb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) udphy_reset_assert(udphy, "pma_apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) udphy_reset_assert(udphy, "pcs_apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static int rk3588_udphy_hpd_event_trigger(struct rockchip_udphy *udphy, bool hpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) udphy->dp_sink_hpd_sel = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) udphy->dp_sink_hpd_cfg = hpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static int rk3588_udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) for (i = 0; i < dp_lanes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) val |= BIT(udphy->dp_lane_sel[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) FIELD_PREP(CMN_DP_LANE_EN_ALL, val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (!dp_lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static int rk3588_udphy_dplane_select(struct rockchip_udphy *udphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) u32 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) switch (udphy->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) case UDPHY_MODE_DP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) value |= 2 << udphy->dp_lane_sel[2] * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) value |= 3 << udphy->dp_lane_sel[3] * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) case UDPHY_MODE_DP_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) value |= 0 << udphy->dp_lane_sel[0] * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) value |= 1 << udphy->dp_lane_sel[1] * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) case UDPHY_MODE_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) regmap_write(udphy->vogrf, udphy->id ? RK3588_GRF_VO0_CON2 : RK3588_GRF_VO0_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static int rk3588_dp_phy_set_rate(struct rockchip_udphy *udphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) switch (dp->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) udphy->bw = DP_BW_RBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) udphy->bw = DP_BW_HBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) udphy->bw = DP_BW_HBR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) udphy->bw = DP_BW_HBR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) FIELD_PREP(CMN_DP_CMN_RSTN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) 0, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) dev_err(udphy->dev, "ROPLL is not lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) u32 voltage, u32 pre, u32 lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) u32 offset = 0x800 * lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) const struct dp_tx_drv_ctrl (*dp_ctrl)[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) dp_ctrl = udphy->mux ? cfg->dp_tx_ctrl_cfg_typec[bw] : cfg->dp_tx_ctrl_cfg[bw];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) val = dp_ctrl[voltage][pre].trsv_reg0204;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) regmap_write(udphy->pma_regmap, 0x0810 + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) val = dp_ctrl[voltage][pre].trsv_reg0205;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) regmap_write(udphy->pma_regmap, 0x0814 + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) val = dp_ctrl[voltage][pre].trsv_reg0206;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) regmap_write(udphy->pma_regmap, 0x0818 + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) val = dp_ctrl[voltage][pre].trsv_reg0207;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) regmap_write(udphy->pma_regmap, 0x081c + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static int rk3588_dp_phy_set_voltages(struct rockchip_udphy *udphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) u32 i, lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) for (i = 0; i < dp->lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) lane = udphy->dp_lane_sel[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) switch (dp->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) LN_ANA_TX_SER_TXCLK_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) udphy->lane_mux_sel[lane]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) LN_ANA_TX_SER_TXCLK_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) rk3588_dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static int __maybe_unused udphy_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct rockchip_udphy *udphy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (udphy->dp_sink_hpd_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) cfg->hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static const struct dev_pm_ops udphy_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, udphy_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static const char * const rk3588_udphy_rst_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) "init", "cmn", "lane", "pcs_apb", "pma_apb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .rst_list = rk3588_udphy_rst_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .grfcfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) /* u2phy-grf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /* usb-grf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /* usbdpphy-grf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .low_pwrn = { 0x0004, 13, 13, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .rx_lfps = { 0x0004, 14, 14, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .vogrfcfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .hpd_trigger = { 0x0000, 11, 10, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .hpd_trigger = { 0x0008, 11, 10, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .dp_tx_ctrl_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) rk3588_dp_tx_drv_ctrl_rbr_hbr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) rk3588_dp_tx_drv_ctrl_rbr_hbr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) rk3588_dp_tx_drv_ctrl_hbr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) rk3588_dp_tx_drv_ctrl_hbr3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .dp_tx_ctrl_cfg_typec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) rk3588_dp_tx_drv_ctrl_hbr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) rk3588_dp_tx_drv_ctrl_hbr3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .combophy_init = rk3588_udphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .dp_phy_set_rate = rk3588_dp_phy_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .dp_phy_set_voltages = rk3588_dp_phy_set_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .hpd_event_trigger = rk3588_udphy_hpd_event_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .dplane_enable = rk3588_udphy_dplane_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .dplane_select = rk3588_udphy_dplane_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static const struct of_device_id rockchip_udphy_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .compatible = "rockchip,rk3588-usbdp-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .data = &rk3588_udphy_cfgs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) MODULE_DEVICE_TABLE(of, rockchip_udphy_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static struct platform_driver rockchip_udphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .probe = rockchip_udphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .name = "rockchip-usbdp-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .of_match_table = rockchip_udphy_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .pm = &udphy_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) module_platform_driver(rockchip_udphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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