^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip usb PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 ROCKCHIP, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/extcon-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/power_supply.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/usb/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/wakelock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int enable_usb_uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HIWORD_UPDATE(val, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ((val) | (mask) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UOC_CON0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UOC_CON0_SIDDQ BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UOC_CON0_DISABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UOC_CON0_COMMON_ON_N BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UOC_CON2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UOC_CON2_SOFT_CON_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UOC_CON3 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* bits present on rk3188 and rk3288 phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UOC_CON3_UTMI_TERMSEL_FULLSPEED BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UOC_CON3_UTMI_XCVRSEELCT_MASK (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UOC_CON3_UTMI_OPMODE_NODRIVING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UOC_CON3_UTMI_OPMODE_MASK (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UOC_CON3_UTMI_SUSPENDN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RK3288_UOC0_CON0 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RK3288_UOC0_CON0_COMMON_ON_N BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RK3288_UOC0_CON0_DISABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RK3288_UOC0_CON2 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RK3288_UOC0_CON2_SOFT_CON_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RK3288_UOC0_CON2_CHRGSEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RK3288_UOC0_CON2_VDATDETENB BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RK3288_UOC0_CON2_VDATSRCENB BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RK3288_UOC0_CON2_DCDENB BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RK3288_UOC0_CON3 0x32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RK3288_UOC0_CON3_UTMI_SUSPENDN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RK3288_UOC0_CON3_UTMI_OPMODE_MASK (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RK3288_UOC0_CON3_BYPASSDMEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RK3288_UOC0_CON3_BYPASSSEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RK3288_UOC0_CON3_IDDIG_SET_OTG (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RK3288_UOC0_CON3_IDDIG_SET_HOST (2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RK3288_UOC0_CON3_IDDIG_SET_PERIPHERAL (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RK3288_UOC0_CON3_IDDIG_SET_MASK (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RK3288_UOC0_CON4 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RK3288_UOC0_CON4_BVALID_IRQ_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RK3288_UOC0_CON4_BVALID_IRQ_PD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RK3288_SOC_STATUS2 0x288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RK3288_SOC_STATUS2_UTMISRP_BVALID BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RK3288_SOC_STATUS2_UTMIOTG_IDDIG BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RK3288_SOC_STATUS19 0x2cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RK3288_SOC_STATUS19_CHGDET BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RK3288_SOC_STATUS19_FSVPLUS BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RK3288_SOC_STATUS19_FSVMINUS BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OTG_SCHEDULE_DELAY (1 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CHG_DCD_MAX_RETRIES 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) enum usb_chg_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) USB_CHG_STATE_UNDEFINED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) USB_CHG_STATE_WAIT_FOR_DCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) USB_CHG_STATE_DCD_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) USB_CHG_STATE_PRIMARY_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) USB_CHG_STATE_SECONDARY_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) USB_CHG_STATE_DETECTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const unsigned int rockchip_usb_phy_extcon_cable[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) EXTCON_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) EXTCON_USB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) EXTCON_USB_VBUS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) EXTCON_CHG_USB_SDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) EXTCON_CHG_USB_CDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) EXTCON_CHG_USB_DCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) EXTCON_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct rockchip_usb_phys {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const char *pll_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct rockchip_usb_phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct rockchip_usb_phy_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct rockchip_usb_phys *phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int (*init_usb_uart)(struct regmap *grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const struct rockchip_usb_phy_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int usb_uart_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct rockchip_usb_phy_base {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct regmap *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct extcon_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const struct rockchip_usb_phy_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct rockchip_usb_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct rockchip_usb_phy_base *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk *clk480m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_hw clk480m_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bool uart_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int bvalid_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct regulator *vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct mutex mutex; /* protects registers of phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct delayed_work chg_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct delayed_work otg_sm_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct wake_lock wakelock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum usb_chg_state chg_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enum power_supply_type chg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) enum usb_dr_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static ssize_t otg_mode_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct rockchip_usb_phy *rk_phy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (!rk_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_err(dev, "Fail to get otg phy.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) switch (rk_phy->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case USB_DR_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return sprintf(buf, "host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case USB_DR_MODE_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return sprintf(buf, "peripheral\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case USB_DR_MODE_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return sprintf(buf, "otg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case USB_DR_MODE_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return sprintf(buf, "UNKNOWN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static ssize_t otg_mode_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct rockchip_usb_phy *rk_phy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) enum usb_dr_mode new_dr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int ret = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!rk_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dev_err(dev, "Fail to get otg phy.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mutex_lock(&rk_phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!strncmp(buf, "0", 1) || !strncmp(buf, "otg", 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) new_dr_mode = USB_DR_MODE_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } else if (!strncmp(buf, "1", 1) || !strncmp(buf, "host", 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) new_dr_mode = USB_DR_MODE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) } else if (!strncmp(buf, "2", 1) || !strncmp(buf, "peripheral", 10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) new_dr_mode = USB_DR_MODE_PERIPHERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_err(&rk_phy->phy->dev, "Error mode! Input 'otg' or 'host' or 'peripheral'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (rk_phy->mode == new_dr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_warn(&rk_phy->phy->dev, "Same as current mode.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rk_phy->mode = new_dr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) switch (rk_phy->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case USB_DR_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) RK3288_UOC0_CON3_IDDIG_SET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) case USB_DR_MODE_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_PERIPHERAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) RK3288_UOC0_CON3_IDDIG_SET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case USB_DR_MODE_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_OTG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) RK3288_UOC0_CON3_IDDIG_SET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mutex_unlock(&rk_phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static DEVICE_ATTR_RW(otg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Group all the usb2 phy attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct attribute *usb2_phy_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) &dev_attr_otg_mode.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct attribute_group usb2_phy_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .name = NULL, /* we want them in the same directory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .attrs = usb2_phy_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) bool siddq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return regmap_write(phy->base->reg_base, phy->reg_offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 480000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct rockchip_usb_phy *phy = container_of(hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct rockchip_usb_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) clk480m_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (phy->vbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) regulator_disable(phy->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Power down usb phy analog blocks by set siddq 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rockchip_usb_phy_power(phy, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct rockchip_usb_phy *phy = container_of(hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct rockchip_usb_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clk480m_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Power up usb phy analog blocks by set siddq 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return rockchip_usb_phy_power(phy, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct rockchip_usb_phy *phy = container_of(hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct rockchip_usb_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clk480m_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return (val & UOC_CON0_SIDDQ) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct clk_ops rockchip_usb_phy480m_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .enable = rockchip_usb_phy480m_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .disable = rockchip_usb_phy480m_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .is_enabled = rockchip_usb_phy480m_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .recalc_rate = rockchip_usb_phy480m_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int rk3288_usb_phy_init(struct phy *_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (phy->bvalid_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mutex_lock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* clear bvalid status and enable bvalid detect irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) val = HIWORD_UPDATE(RK3288_UOC0_CON4_BVALID_IRQ_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) | RK3288_UOC0_CON4_BVALID_IRQ_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) RK3288_UOC0_CON4_BVALID_IRQ_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) | RK3288_UOC0_CON4_BVALID_IRQ_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = regmap_write(phy->base->reg_base, RK3288_UOC0_CON4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_err(phy->base->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "failed to enable bvalid irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) schedule_delayed_work(&phy->otg_sm_work, OTG_SCHEDULE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mutex_unlock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int rk3288_usb_phy_exit(struct phy *_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (phy->bvalid_irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) flush_delayed_work(&phy->otg_sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int rockchip_usb_phy_power_off(struct phy *_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (phy->uart_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) clk_disable_unprepare(phy->clk480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int rockchip_usb_phy_power_on(struct phy *_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (phy->uart_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (phy->vbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = regulator_enable(phy->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return clk_prepare_enable(phy->clk480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int rockchip_usb_phy_reset(struct phy *_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (phy->reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) reset_control_assert(phy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) reset_control_deassert(phy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static struct phy_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .power_on = rockchip_usb_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .power_off = rockchip_usb_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .reset = rockchip_usb_phy_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void rockchip_usb_phy_action(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct rockchip_usb_phy *rk_phy = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!rk_phy->uart_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) of_clk_del_provider(rk_phy->np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) clk_unregister(rk_phy->clk480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (rk_phy->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) clk_put(rk_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int rockchip_usb_phy_extcon_register(struct rockchip_usb_phy_base *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct device_node *node = base->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct extcon_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (of_property_read_bool(node, "extcon")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) edev = extcon_get_edev_by_phandle(base->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (IS_ERR(edev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (PTR_ERR(edev) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(base->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "Invalid or missing extcon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return PTR_ERR(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Initialize extcon device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) edev = devm_extcon_dev_allocate(base->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) rockchip_usb_phy_extcon_cable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (IS_ERR(edev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = devm_extcon_dev_register(base->dev, edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(base->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "failed to register extcon device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) base->edev = edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void rk3288_usb_phy_otg_sm_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct rockchip_usb_phy *rk_phy = container_of(work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct rockchip_usb_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) otg_sm_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static unsigned int cable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static bool chg_det_completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) bool sch_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) bool vbus_attached;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) bool id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) mutex_lock(&rk_phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sch_work = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) id = (val & RK3288_SOC_STATUS2_UTMIOTG_IDDIG) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) vbus_attached =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) (val & RK3288_SOC_STATUS2_UTMISRP_BVALID) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!vbus_attached || !id || rk_phy->mode == USB_DR_MODE_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_dbg(&rk_phy->phy->dev, "peripheral disconnected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) wake_unlock(&rk_phy->wakelock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) extcon_set_state_sync(rk_phy->base->edev, cable, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) rk_phy->chg_state = USB_CHG_STATE_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) chg_det_completed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (chg_det_completed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) sch_work = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) switch (rk_phy->chg_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case USB_CHG_STATE_UNDEFINED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mutex_unlock(&rk_phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) schedule_delayed_work(&rk_phy->chg_work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case USB_CHG_STATE_DETECTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) switch (rk_phy->chg_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case POWER_SUPPLY_TYPE_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev_dbg(&rk_phy->phy->dev, "sdp cable is connected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) wake_lock(&rk_phy->wakelock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) cable = EXTCON_CHG_USB_SDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) sch_work = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case POWER_SUPPLY_TYPE_USB_DCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev_dbg(&rk_phy->phy->dev, "dcp cable is connected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) cable = EXTCON_CHG_USB_DCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) sch_work = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case POWER_SUPPLY_TYPE_USB_CDP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_dbg(&rk_phy->phy->dev, "cdp cable is connected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) wake_lock(&rk_phy->wakelock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) cable = EXTCON_CHG_USB_CDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sch_work = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) chg_det_completed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (extcon_get_state(rk_phy->base->edev, cable) != vbus_attached)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) extcon_set_state_sync(rk_phy->base->edev, cable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) vbus_attached);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (sch_work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) schedule_delayed_work(&rk_phy->otg_sm_work, OTG_SCHEDULE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mutex_unlock(&rk_phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const char *chg_to_string(enum power_supply_type chg_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) switch (chg_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case POWER_SUPPLY_TYPE_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return "USB_SDP_CHARGER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case POWER_SUPPLY_TYPE_USB_DCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return "USB_DCP_CHARGER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case POWER_SUPPLY_TYPE_USB_CDP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return "USB_CDP_CHARGER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return "INVALID_CHARGER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static void rk3288_chg_detect_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct rockchip_usb_phy *rk_phy =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) container_of(work, struct rockchip_usb_phy, chg_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int dcd_retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int primary_retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned long delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) bool fsvplus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) bool vout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bool tmout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_dbg(&rk_phy->phy->dev, "chg detection work state = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) rk_phy->chg_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) switch (rk_phy->chg_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case USB_CHG_STATE_UNDEFINED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mutex_lock(&rk_phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* put the controller in non-driving mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) RK3288_UOC0_CON2_SOFT_CON_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) RK3288_UOC0_CON3_UTMI_SUSPENDN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) | RK3288_UOC0_CON3_UTMI_OPMODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Start DCD processing stage 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) val = HIWORD_UPDATE(RK3288_UOC0_CON2_DCDENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) RK3288_UOC0_CON2_DCDENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) rk_phy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dcd_retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) primary_retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) delay = CHG_DCD_POLL_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case USB_CHG_STATE_WAIT_FOR_DCD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* get data contact detection status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS19, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) fsvplus = (val & RK3288_SOC_STATUS19_FSVPLUS) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) tmout = ++dcd_retries == CHG_DCD_MAX_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* stage 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!fsvplus || tmout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) vdpsrc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* stage 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Turn off DCD circuitry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_DCDENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) regmap_write(rk_phy->base->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) RK3288_UOC0_CON2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Voltage Source on DP, Probe on DM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) val = HIWORD_UPDATE(RK3288_UOC0_CON2_VDATSRCENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) | RK3288_UOC0_CON2_VDATDETENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) RK3288_UOC0_CON2_VDATSRCENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) | RK3288_UOC0_CON2_VDATDETENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) | RK3288_UOC0_CON2_CHRGSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) regmap_write(rk_phy->base->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) RK3288_UOC0_CON2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) delay = CHG_PRIMARY_DET_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) rk_phy->chg_state = USB_CHG_STATE_DCD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* stage 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) delay = CHG_DCD_POLL_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case USB_CHG_STATE_DCD_DONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS19, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) vout = (val & RK3288_SOC_STATUS19_CHGDET) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_VDATSRCENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) | RK3288_UOC0_CON2_VDATDETENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (vout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Voltage Source on DM, Probe on DP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) val = HIWORD_UPDATE(RK3288_UOC0_CON2_VDATSRCENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) | RK3288_UOC0_CON2_VDATDETENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) | RK3288_UOC0_CON2_CHRGSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) RK3288_UOC0_CON2_VDATSRCENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) | RK3288_UOC0_CON2_VDATDETENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) | RK3288_UOC0_CON2_CHRGSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) regmap_write(rk_phy->base->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) RK3288_UOC0_CON2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) delay = CHG_SECONDARY_DET_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rk_phy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (dcd_retries == CHG_DCD_MAX_RETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* floating charger found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) rk_phy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) rk_phy->chg_state = USB_CHG_STATE_DETECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) } else if (primary_retries < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) primary_retries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) goto vdpsrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) rk_phy->chg_type = POWER_SUPPLY_TYPE_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) rk_phy->chg_state = USB_CHG_STATE_DETECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case USB_CHG_STATE_PRIMARY_DONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS19, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) vout = (val & RK3288_SOC_STATUS19_CHGDET) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Turn off voltage source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_VDATSRCENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) | RK3288_UOC0_CON2_VDATDETENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) | RK3288_UOC0_CON2_CHRGSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (vout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) rk_phy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) rk_phy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case USB_CHG_STATE_SECONDARY_DONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) rk_phy->chg_state = USB_CHG_STATE_DETECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) case USB_CHG_STATE_DETECTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* put the controller in normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_SOFT_CON_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_SUSPENDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) RK3288_UOC0_CON3_UTMI_SUSPENDN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) | RK3288_UOC0_CON3_UTMI_OPMODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) mutex_unlock(&rk_phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) rk3288_usb_phy_otg_sm_work(&rk_phy->otg_sm_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_info(&rk_phy->phy->dev, "charger = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) chg_to_string(rk_phy->chg_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mutex_unlock(&rk_phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * Hold the mutex lock during the whole charger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * detection stage, and release it after detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * the charger type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) schedule_delayed_work(&rk_phy->chg_work, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static irqreturn_t rk3288_usb_phy_bvalid_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct rockchip_usb_phy *rk_phy = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = regmap_read(rk_phy->base->reg_base, RK3288_UOC0_CON4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret < 0 || !(val & RK3288_UOC0_CON4_BVALID_IRQ_PD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) mutex_lock(&rk_phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* clear bvalid detect irq pending status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) val = HIWORD_UPDATE(RK3288_UOC0_CON4_BVALID_IRQ_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) RK3288_UOC0_CON4_BVALID_IRQ_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) mutex_unlock(&rk_phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (rk_phy->uart_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) cancel_delayed_work_sync(&rk_phy->otg_sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) rk3288_usb_phy_otg_sm_work(&rk_phy->otg_sm_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int rk3288_usb_phy_probe_init(struct rockchip_usb_phy *rk_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (rk_phy->reg_offset == 0x320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Enable Bvalid interrupt and charge detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ops.init = rk3288_usb_phy_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ops.exit = rk3288_usb_phy_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) rk_phy->bvalid_irq = of_irq_get_byname(rk_phy->np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) "otg-bvalid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) regmap_read(rk_phy->base->reg_base, RK3288_UOC0_CON4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (rk_phy->bvalid_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_err(&rk_phy->phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "no vbus valid irq provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = devm_request_threaded_irq(rk_phy->base->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) rk_phy->bvalid_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) rk3288_usb_phy_bvalid_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "rockchip_usb_phy_bvalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) rk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev_err(&rk_phy->phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "failed to request otg-bvalid irq handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) rk_phy->chg_state = USB_CHG_STATE_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) wake_lock_init(&rk_phy->wakelock, WAKE_LOCK_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "rockchip_otg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) INIT_DELAYED_WORK(&rk_phy->chg_work, rk3288_chg_detect_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) INIT_DELAYED_WORK(&rk_phy->otg_sm_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) rk3288_usb_phy_otg_sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) rk_phy->mode = of_usb_get_dr_mode_by_phy(rk_phy->np, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (rk_phy->mode == USB_DR_MODE_OTG ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) rk_phy->mode == USB_DR_MODE_UNKNOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = sysfs_create_group(&rk_phy->phy->dev.kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) &usb2_phy_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_err(&rk_phy->phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "Cannot create sysfs group\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) } else if (rk_phy->reg_offset == 0x334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * Setting the COMMONONN to 1'b0 for EHCI PHY on RK3288 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * EHCI (auto) suspend causes the corresponding usb-phy into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * suspend mode which would power down the inner PLL blocks in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * usb-phy if the COMMONONN is set to 1'b1. The PLL output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * clocks contained CLK480M, CLK12MOHCI, CLK48MOHCI, PHYCLOCK0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * and so on, these clocks are not only supplied for EHCI and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * OHCI, but also supplied for GPU and other external modules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * so setting COMMONONN to 1'b0 to keep the inner PLL blocks in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * usb-phy always powered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) regmap_write(rk_phy->base->reg_base, rk_phy->reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) BIT(16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct device_node *child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct device_node *np = base->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct rockchip_usb_phy *rk_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) unsigned int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!rk_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) rk_phy->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) rk_phy->np = child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mutex_init(&rk_phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (of_property_read_u32(child, "reg", ®_offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_err(base->dev, "missing reg property in node %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) rk_phy->reset = of_reset_control_get(child, "phy-reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (IS_ERR(rk_phy->reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) rk_phy->reset = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) rk_phy->reg_offset = reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) rk_phy->clk = of_clk_get_by_name(child, "phyclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (IS_ERR(rk_phy->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) rk_phy->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) init.name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) while (base->pdata->phys[i].reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (base->pdata->phys[i].reg == reg_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) init.name = base->pdata->phys[i].pll_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!init.name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_err(base->dev, "phy data not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (enable_usb_uart && base->pdata->usb_uart_phy == i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev_dbg(base->dev, "phy%d used as uart output\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) rk_phy->uart_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (rk_phy->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) clk_name = __clk_get_name(rk_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) init.parent_names = &clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) init.ops = &rockchip_usb_phy480m_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) rk_phy->clk480m_hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (IS_ERR(rk_phy->clk480m)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) err = PTR_ERR(rk_phy->clk480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) err = of_clk_add_provider(child, of_clk_src_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) rk_phy->clk480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) goto err_clk_prov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) err = devm_add_action_or_reset(base->dev, rockchip_usb_phy_action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) rk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) rk_phy->phy = devm_phy_create(base->dev, child, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (IS_ERR(rk_phy->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev_err(base->dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return PTR_ERR(rk_phy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) phy_set_drvdata(rk_phy->phy, rk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (of_device_is_compatible(np, "rockchip,rk3288-usb-phy")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) err = rk3288_usb_phy_probe_init(rk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) rk_phy->vbus = devm_regulator_get_optional(&rk_phy->phy->dev, "vbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (IS_ERR(rk_phy->vbus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (PTR_ERR(rk_phy->vbus) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return PTR_ERR(rk_phy->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) rk_phy->vbus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * When acting as uart-pipe, just keep clock on otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * only power up usb phy when it use, so disable it when init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (rk_phy->uart_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return clk_prepare_enable(rk_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return rockchip_usb_phy_power(rk_phy, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) err_clk_prov:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (!rk_phy->uart_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) clk_unregister(rk_phy->clk480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (rk_phy->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) clk_put(rk_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .phys = (struct rockchip_usb_phys[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) { .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) { .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int __init rockchip_init_usb_uart_common(struct regmap *grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) const struct rockchip_usb_phy_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int regoffs = pdata->phys[pdata->usb_uart_phy].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * COMMON_ON and DISABLE settings are described in the TRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * but were not present in the original code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * Also disable the analog phy components to save power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) | UOC_CON0_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) | UOC_CON0_SIDDQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) UOC_CON0_COMMON_ON_N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) | UOC_CON0_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) | UOC_CON0_SIDDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ret = regmap_write(grf, regoffs + UOC_CON0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) UOC_CON2_SOFT_CON_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ret = regmap_write(grf, regoffs + UOC_CON2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) | UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) | UOC_CON3_UTMI_TERMSEL_FULLSPEED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) UOC_CON3_UTMI_SUSPENDN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) | UOC_CON3_UTMI_OPMODE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) | UOC_CON3_UTMI_XCVRSEELCT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) | UOC_CON3_UTMI_TERMSEL_FULLSPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = regmap_write(grf, UOC_CON3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define RK3188_UOC0_CON0 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define RK3188_UOC0_CON0_BYPASSSEL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define RK3188_UOC0_CON0_BYPASSDMEN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * Enable the bypass of uart2 data through the otg usb phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * See description of rk3288-variant for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int __init rk3188_init_usb_uart(struct regmap *grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) const struct rockchip_usb_phy_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = rockchip_init_usb_uart_common(grf, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) | RK3188_UOC0_CON0_BYPASSDMEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) RK3188_UOC0_CON0_BYPASSSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) | RK3188_UOC0_CON0_BYPASSDMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ret = regmap_write(grf, RK3188_UOC0_CON0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static const struct rockchip_usb_phy_pdata rk3188_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .phys = (struct rockchip_usb_phys[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) { .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) { .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .init_usb_uart = rk3188_init_usb_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .usb_uart_phy = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * Enable the bypass of uart2 data through the otg usb phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * Original description in the TRM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * 2. Disable the pull-up resistance on the D+ line by setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * OPMODE0[1:0] to 2’b01.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * mode, set COMMONONN to 1’b1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * 5. Set BYPASSSEL0 to 1’b1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * To receive data, monitor FSVPLUS0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * The actual code in the vendor kernel does some things differently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static int __init rk3288_init_usb_uart(struct regmap *grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) const struct rockchip_usb_phy_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ret = rockchip_init_usb_uart_common(grf, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) | RK3288_UOC0_CON3_BYPASSDMEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) RK3288_UOC0_CON3_BYPASSSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) | RK3288_UOC0_CON3_BYPASSDMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret = regmap_write(grf, RK3288_UOC0_CON3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static const struct rockchip_usb_phy_pdata rk3288_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .phys = (struct rockchip_usb_phys[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) { .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) { .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) { .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .init_usb_uart = rk3288_init_usb_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .usb_uart_phy = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int rockchip_usb_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct rockchip_usb_phy_base *phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!phy_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) match = of_match_device(dev->driver->of_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (!match || !match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev_err(dev, "missing phy data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) phy_base->pdata = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) phy_base->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) phy_base->reg_base = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (dev->parent && dev->parent->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) phy_base->reg_base = syscon_node_to_regmap(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (IS_ERR(phy_base->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) phy_base->reg_base = syscon_regmap_lookup_by_phandle(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dev->of_node, "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (IS_ERR(phy_base->reg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev_err(&pdev->dev, "Missing rockchip,grf property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return PTR_ERR(phy_base->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) err = rockchip_usb_phy_extcon_register(phy_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) for_each_available_child_of_node(dev->of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) err = rockchip_usb_phy_init(phy_base, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) { .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) { .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static struct platform_driver rockchip_usb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .probe = rockchip_usb_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .name = "rockchip-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .of_match_table = rockchip_usb_phy_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) module_platform_driver(rockchip_usb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static int __init rockchip_init_usb_uart(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) const struct rockchip_usb_phy_pdata *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (!enable_usb_uart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) np = of_find_matching_node_and_match(NULL, rockchip_usb_phy_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) &match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) pr_err("%s: failed to find usbphy node\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) pr_debug("%s: using settings for %s\n", __func__, match->compatible);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (!data->init_usb_uart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) pr_err("%s: usb-uart not available on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) __func__, match->compatible);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) grf = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (np->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) grf = syscon_node_to_regmap(np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (IS_ERR(grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) pr_err("%s: Missing rockchip,grf property, %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) __func__, PTR_ERR(grf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return PTR_ERR(grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = data->init_usb_uart(grf, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) pr_err("%s: could not init usb_uart, %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) enable_usb_uart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) early_initcall(rockchip_init_usb_uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static int __init rockchip_usb_uart(char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) enable_usb_uart = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) early_param("rockchip.usb_uart", rockchip_usb_uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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