^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip PCIE3.0 phy driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy/pcie.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/phy/phy-snps-pcie3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Register for RK3568 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GRF_PCIE30PHY_CON1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GRF_PCIE30PHY_CON6 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GRF_PCIE30PHY_CON9 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GRF_PCIE30PHY_STATUS0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SRAM_INIT_DONE(reg) (reg & BIT(14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Register for RK3588 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PHP_GRF_PCIESEL_CON 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct rockchip_p3phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct rockchip_p3phy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) const struct rockchip_p3phy_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* mode: RC, EP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* pcie30_phymode: Aggregation, Bifurcation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int pcie30_phymode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct regmap *phy_grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct regmap *pipe_grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct reset_control *p30phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bool is_bifurcation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct rockchip_p3phy_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int (*phy_init)(struct rockchip_p3phy_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Acutally We don't care EP/RC mode, but just record it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) switch (submode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case PHY_MODE_PCIE_RC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) priv->mode = PHY_MODE_PCIE_RC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case PHY_MODE_PCIE_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) priv->mode = PHY_MODE_PCIE_EP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case PHY_MODE_PCIE_BIFURCATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) priv->is_bifurcation = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pr_info("%s, invalid mode\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Deassert PCIe PMA output clamp mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) (0x1 << 15) | (0x1 << 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Set bifurcation if needed, and it doesn't care RC/EP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (priv->is_bifurcation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0x1 | (0xf << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) (0x1 << 15) | (0x1 << 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reset_control_deassert(priv->p30phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Updata RX VCO calibration controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(0x2800, priv->mmio + (0x104a << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writel(0x2800, priv->mmio + (0x114a << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = regmap_read_poll_timeout(priv->phy_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GRF_PCIE30PHY_STATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reg, SRAM_INIT_DONE(reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct rockchip_p3phy_ops rk3568_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .phy_init = rockchip_p3phy_rk3568_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Deassert PCIe PMA output clamp mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) (0x1 << 8) | (0x1 << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) reset_control_deassert(priv->p30phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = regmap_read_poll_timeout(priv->phy_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) reg, RK3588_SRAM_INIT_DONE(reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret |= regmap_read_poll_timeout(priv->phy_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) reg, RK3588_SRAM_INIT_DONE(reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct rockchip_p3phy_ops rk3588_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .phy_init = rockchip_p3phy_rk3588_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int rochchip_p3phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pr_err("failed to enable PCIe bulk clks %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) reset_control_assert(priv->p30phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (priv->ops->phy_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret = priv->ops->phy_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int rochchip_p3phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) reset_control_assert(priv->p30phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct phy_ops rochchip_p3phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .init = rochchip_p3phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .exit = rochchip_p3phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .set_mode = rockchip_p3phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int rockchip_p3phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct rockchip_p3phy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) priv->mmio = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (IS_ERR(priv->mmio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = PTR_ERR(priv->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) priv->ops = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!priv->ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_err(&pdev->dev, "no of match data provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (IS_ERR(priv->phy_grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return PTR_ERR(priv->phy_grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "rockchip,pipe-grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (IS_ERR(priv->pipe_grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = device_property_read_u32(dev, "rockchip,pcie30-phymode", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) priv->pcie30_phymode = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Select correct pcie30_phymode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (priv->pcie30_phymode > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (0x7<<16) | priv->pcie30_phymode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!IS_ERR(priv->pipe_grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) reg = priv->pcie30_phymode & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) (reg << 16) | reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (IS_ERR(priv->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(dev, "failed to create combphy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return PTR_ERR(priv->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) priv->p30phy = devm_reset_control_get(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (IS_ERR(priv->p30phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_warn(dev, "no phy reset control specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) priv->p30phy = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (priv->num_clks < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) phy_set_drvdata(priv->phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const struct of_device_id rockchip_p3phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct platform_driver rockchip_p3phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .probe = rockchip_p3phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .name = "rockchip-snps-pcie3-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .of_match_table = rockchip_p3phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) module_platform_driver(rockchip_p3phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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