^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip HDMI/DP Combo PHY with Samsung IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HDPTXPHY_GRF_CON0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RO_REF_CLK_SEL GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LC_REF_CLK_SEL GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BIAS_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BGR_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HDPTX_MODE_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HDPTXPHY_GRF_STATUS0 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLL_LOCK_DONE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PHY_CLK_RDY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PHY_RDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SB_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* cmn_reg0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OVRD_LCPLL_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LCPLL_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* cmn_reg003C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ANA_LCPLL_RESERVED7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* cmn_reg003D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OVRD_ROPLL_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ROPLL_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* cmn_reg0046 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* cmn_reg0047 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* cmn_reg004E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ANA_ROPLL_PI_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* cmn_reg0051 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ROPLL_PMS_MDIV GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* cmn_reg0055 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* cmn_reg0059 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* cmn_reg005A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ROPLL_PMS_SDIV_HBR GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* cmn_reg005B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ROPLL_PMS_SDIV_HBR3 GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* cmn_reg005D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OVRD_ROPLL_REF_CLK_SEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ROPLL_REF_CLK_SEL GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* cmn_reg005E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ANA_ROPLL_SDM_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OVRD_ROPLL_SDM_RSTN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ROPLL_SDM_RSTN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ROPLL_SDC_FRACTIONAL_EN_RBR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ROPLL_SDC_FRACTIONAL_EN_HBR2 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ROPLL_SDC_FRACTIONAL_EN_HBR3 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* cmn_reg005F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OVRD_ROPLL_SDC_RSTN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ROPLL_SDC_RSTN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* cmn_reg0060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ROPLL_SDM_DENOMINATOR GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* cmn_reg0064 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ROPLL_SDM_NUMERATOR_SIGN_RBR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ROPLL_SDM_NUMERATOR_SIGN_HBR2 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ROPLL_SDM_NUMERATOR_SIGN_HBR3 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* cmn_reg0065 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ROPLL_SDM_NUMERATOR GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* cmn_reg0069 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ROPLL_SDC_N_RBR GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* cmn_reg006A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ROPLL_SDC_N_HBR GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ROPLL_SDC_N_HBR2 GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* cmn_reg006B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ROPLL_SDC_N_HBR3 GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* cmn_reg006C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ROPLL_SDC_NUMERATOR GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* cmn_reg0070 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ROPLL_SDC_DENOMINATOR GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* cmn_reg0074 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OVRD_ROPLL_SDC_NDIV_RSTN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ROPLL_SDC_NDIV_RSTN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OVRD_ROPLL_SSC_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ROPLL_SSC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* cmn_reg0075 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ANA_ROPLL_SSC_FM_DEVIATION GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* cmn_reg0076 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* cmn_reg0077 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ANA_ROPLL_SSC_CLK_DIV_SEL GENMASK(6, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* cmn_reg0081 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ANA_PLL_CD_TX_SER_RATE_SEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ANA_PLL_CD_HSCLK_WEST_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ANA_PLL_CD_HSCLK_EAST_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* cmn_reg0082 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ANA_PLL_CD_VREG_GAIN_CTRL GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* cmn_reg0083 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ANA_PLL_CD_VREG_ICTRL GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* cmn_reg0084 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PLL_LCRO_CLK_SEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* cmn_reg0085 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ANA_PLL_SYNC_LOSS_DET_MODE GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* cmn_reg0087 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ANA_PLL_TX_HS_CLK_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* cmn_reg0095 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DP_TX_LINK_BW GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* cmn_reg0097 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DIG_CLK_SEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* cmn_reg0099 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SSC_EN GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CMN_ROPLL_ALONE_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* cmn_reg009A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HS_SPEED_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* cmn_reg009B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LS_SPEED_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* sb_reg0102 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OVRD_SB_RXTERM_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SB_RXRERM_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ANA_SB_RXTERM_OFFSP GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* sb_reg0103 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ANA_SB_RXTERM_OFFSN GENMASK(6, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OVRD_SB_RX_RESCAL_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SB_RX_RESCAL_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* sb_reg0104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OVRD_SB_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SB_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OVRD_SB_AUX_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SB_AUX_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* sb_reg0105 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ANA_SB_TX_HLVL_PROG GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* sb_reg0106 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ANA_SB_TX_LLVL_PROG GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* sb_reg010D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ANA_SB_DMRX_LPBK_DATA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* sb_reg010F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OVRD_SB_VREG_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SB_VREG_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* sb_reg0110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ANA_SB_VREG_OUT_SEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ANA_SB_VREG_REF_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* sb_reg0113 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SB_RX_RCAL_OPT_CODE GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SB_RX_RTERM_CTRL GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* sb_reg0114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SB_TG_SB_EN_DELAY_TIME GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SB_TG_RXTERN_EN_DELAY_TIME GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* sb_reg0115 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SB_READY_DELAY_TIME GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SB_TG_OSC_EN_DELAY_TIME GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* sb_reg0116 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* sb_reg0117 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SB_TG_PLL_CD_VREG_FAST_PULSE_TIME GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* sb_reg0118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* sb_reg011A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SB_TG_CNT_RUN_NO_7_0 GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* sb_reg011B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SB_EARC_SIG_DET_BYPASS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SB_AFC_TOL GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* sb_reg011C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SB_AFC_STB_NUM GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* sb_reg011D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SB_TG_OSC_CNT_MIN GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* sb_reg011E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SB_TG_OSC_CNT_MAX GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* sb_reg011F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SB_PWM_AFC_CTRL GENMASK(7, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SB_RCAL_RSTN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* sb_reg0120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SB_AUX_EN_IN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* sb_reg0123 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define OVRD_SB_READY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SB_READY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* lntop_reg0200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PROTOCOL_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* lntop_reg0206 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DATA_BUS_WIDTH GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define BUS_WIDTH_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* lntop_reg0207 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define LANE_EN GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* lane_reg0301 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define OVRD_LN_TX_DRV_EI_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define LN_TX_DRV_EI_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* lane_reg0303 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define OVRD_LN_TX_DRV_LVL_CTRL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define LN_TX_DRV_LVL_CTRL GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* lane_reg0304 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define OVRD_LN_TX_DRV_POST_LVL_CTRL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* lane_reg0305 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OVRD_LN_TX_DRV_PRE_LVL_CTRL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define LN_TX_DRV_PRE_LVL_CTRL GENMASK(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* lane_reg0306 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define LN_ANA_TX_DRV_IDRV_IDN_CTRL GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define LN_ANA_TX_DRV_IDRV_IUP_CTRL GENMASK(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define LN_ANA_TX_DRV_ACCDRV_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* lane_reg0307 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define LN_ANA_TX_DRV_ACCDRV_POL_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define LN_ANA_TX_DRV_ACCDRV_CTRL GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* lane_reg030A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define LN_ANA_TX_JEQ_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define LN_TX_JEQ_EVEN_CTRL_RBR GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* lane_reg030B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define LN_TX_JEQ_EVEN_CTRL_HBR2 GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* lane_reg030C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define LN_TX_JEQ_ODD_CTRL_RBR GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* lane_reg030D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define LN_TX_JEQ_ODD_CTRL_HBR2 GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* lane_reg030E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* lane_reg0310 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define LN_ANA_TX_SYNC_LOSS_DET_MODE GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* lane_reg0311 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define LN_TX_SER_40BIT_EN_RBR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define LN_TX_SER_40BIT_EN_HBR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define LN_TX_SER_40BIT_EN_HBR2 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define LN_TX_SER_40BIT_EN_HBR3 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* lane_reg0316 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define LN_ANA_TX_SER_VREG_GAIN_CTRL GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* lane_reg031B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define LN_ANA_TX_RESERVED GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* lane_reg031E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define LN_POLARITY_INV BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define LANE_REG(lane, offset) (0x400 * (lane) + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct rockchip_hdptx_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int nr_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct reset_control *apb_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct reset_control *cmn_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct reset_control *init_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct reset_control *lane_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 lane_polarity_invert[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DP_BW_RBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) DP_BW_HBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DP_BW_HBR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DP_BW_HBR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct tx_drv_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 tx_drv_lvl_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 tx_drv_post_lvl_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 ana_tx_drv_idrv_idn_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 ana_tx_drv_idrv_iup_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 ana_tx_drv_accdrv_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 ana_tx_drv_accdrv_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* voltage swing 0, pre-emphasis 0->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { 0x1, 0x0, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* voltage swing 1, pre-emphasis 0->2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { 0xa, 0x5, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* voltage swing 2, pre-emphasis 0->1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { 0xd, 0x5, 0x7, 0x7, 0x1, 0x7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* voltage swing 3, pre-emphasis 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* voltage swing 0, pre-emphasis 0->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* voltage swing 1, pre-emphasis 0->2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 0xb, 0x6, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* voltage swing 2, pre-emphasis 0->1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* voltage swing 3, pre-emphasis 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { 0xd, 0x1, 0x7, 0x7, 0x1, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* voltage swing 0, pre-emphasis 0->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* voltage swing 1, pre-emphasis 0->2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { 0xc, 0x7, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* voltage swing 2, pre-emphasis 0->1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* voltage swing 3, pre-emphasis 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int rockchip_hdptx_phy_parse_training_table(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) size_t size = sizeof(struct tx_drv_ctrl) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 *buf, *training_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) buf = kzalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (device_property_read_u8_array(dev, "training-table", buf, size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) training_table = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for (j = 0; j < 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct tx_drv_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (i + j > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ctrl = (struct tx_drv_ctrl *)training_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) tx_drv_ctrl_rbr[i][j] = *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tx_drv_ctrl_hbr[i][j] = *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tx_drv_ctrl_hbr2[i][j] = *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) training_table += sizeof(*ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int rockchip_grf_write(struct regmap *grf, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned int mask, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return regmap_write(grf, reg, (mask << 16) | (val & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy *hdptx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (dp->set_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) switch (dp->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) switch (dp->lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (dp->set_voltages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) for (i = 0; i < dp->lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (dp->voltage[i] > 3 || dp->pre[i] > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (dp->voltage[i] + dp->pre[i] > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct phy_configure_opts_dp *dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) const struct tx_drv_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) switch (dp->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) LN_TX_SER_40BIT_EN_RBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) LN_TX_SER_40BIT_EN_HBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) LN_TX_SER_40BIT_EN_HBR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) OVRD_LN_TX_DRV_LVL_CTRL | LN_TX_DRV_LVL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) FIELD_PREP(LN_TX_DRV_LVL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ctrl->tx_drv_lvl_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) OVRD_LN_TX_DRV_POST_LVL_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) LN_TX_DRV_POST_LVL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ctrl->tx_drv_post_lvl_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) LN_ANA_TX_DRV_IDRV_IDN_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) LN_ANA_TX_DRV_IDRV_IUP_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) LN_ANA_TX_DRV_ACCDRV_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ctrl->ana_tx_drv_idrv_idn_ctrl) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ctrl->ana_tx_drv_idrv_iup_ctrl) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ctrl->ana_tx_drv_accdrv_en));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) LN_ANA_TX_DRV_ACCDRV_POL_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) LN_ANA_TX_DRV_ACCDRV_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ctrl->ana_tx_drv_accdrv_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c6c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) LN_ANA_TX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) FIELD_PREP(LN_ANA_TX_RESERVED, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) LN_ANA_TX_SER_VREG_GAIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL, 0x2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) LN_ANA_TX_SYNC_LOSS_DET_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE, 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy *hdptx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u8 lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) for (lane = 0; lane < dp->lanes; lane++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) rockchip_hdptx_phy_set_voltage(hdptx, dp, lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static void rockchip_hdptx_phy_lane_disable(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) reset_control_assert(hdptx->lane_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) FIELD_PREP(LANE_EN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) FIELD_PREP(PLL_EN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) regmap_update_bits(hdptx->regmap, 0x0020, OVRD_LCPLL_EN | LCPLL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) FIELD_PREP(OVRD_LCPLL_EN, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) FIELD_PREP(LCPLL_EN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) regmap_update_bits(hdptx->regmap, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) FIELD_PREP(OVRD_ROPLL_EN, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) FIELD_PREP(ROPLL_EN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int rockchip_hdptx_phy_set_lanes(struct rockchip_hdptx_phy *hdptx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!dp->lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) rockchip_hdptx_phy_lane_disable(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) reset_control_deassert(hdptx->lane_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) status, FIELD_GET(PHY_RDY, status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 50, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dev_err(hdptx->dev, "timeout waiting for phy_rdy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy *hdptx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 bw, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) FIELD_PREP(PLL_EN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) switch (dp->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) bw = DP_BW_RBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) bw = DP_BW_HBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) bw = DP_BW_HBR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) regmap_update_bits(hdptx->regmap, 0x0254, DP_TX_LINK_BW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) FIELD_PREP(DP_TX_LINK_BW, bw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (dp->ssc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) regmap_update_bits(hdptx->regmap, 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) FIELD_PREP(ROPLL_SSC_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) regmap_write(hdptx->regmap, 0x01d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0xc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) regmap_update_bits(hdptx->regmap, 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ANA_ROPLL_SSC_FM_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) FIELD_PREP(SSC_EN, 0x2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) regmap_update_bits(hdptx->regmap, 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) FIELD_PREP(ROPLL_SSC_EN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) regmap_write(hdptx->regmap, 0x01d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0x20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) regmap_update_bits(hdptx->regmap, 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ANA_ROPLL_SSC_FM_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0xc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) FIELD_PREP(SSC_EN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) regmap_update_bits(hdptx->regmap, 0x0020, OVRD_LCPLL_EN | LCPLL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) FIELD_PREP(OVRD_LCPLL_EN, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) FIELD_PREP(LCPLL_EN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) regmap_update_bits(hdptx->regmap, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) FIELD_PREP(OVRD_ROPLL_EN, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) FIELD_PREP(ROPLL_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) FIELD_PREP(PLL_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) status, FIELD_GET(PLL_LOCK_DONE, status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 50, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_err(hdptx->dev, "timeout waiting for pll_lock_done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static int rockchip_hdptx_phy_configure(struct phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) union phy_configure_opts *opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) enum phy_mode mode = phy_get_mode(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (mode != PHY_MODE_DP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ret = rockchip_hdptx_phy_verify_config(hdptx, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_err(hdptx->dev, "invalid params for phy configure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (opts->dp.set_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = rockchip_hdptx_phy_set_rate(hdptx, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_err(hdptx->dev, "failed to set rate: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (opts->dp.set_lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret = rockchip_hdptx_phy_set_lanes(hdptx, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_err(hdptx->dev, "failed to set lanes: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (opts->dp.set_voltages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ret = rockchip_hdptx_phy_set_voltages(hdptx, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_err(hdptx->dev, "failed to set voltages: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static void rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) regmap_write(hdptx->regmap, 0x0144, FIELD_PREP(ROPLL_PMS_MDIV, 0x87));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) regmap_write(hdptx->regmap, 0x0148, FIELD_PREP(ROPLL_PMS_MDIV, 0x71));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) regmap_write(hdptx->regmap, 0x014c, FIELD_PREP(ROPLL_PMS_MDIV, 0x71));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) regmap_write(hdptx->regmap, 0x0154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x87));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) regmap_write(hdptx->regmap, 0x0158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) regmap_write(hdptx->regmap, 0x015c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) regmap_write(hdptx->regmap, 0x0164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) FIELD_PREP(ANA_ROPLL_PMS_PDIV, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) FIELD_PREP(ANA_ROPLL_PMS_REFDIV, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) regmap_write(hdptx->regmap, 0x0168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) FIELD_PREP(ROPLL_PMS_SDIV_RBR, 0x3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) FIELD_PREP(ROPLL_PMS_SDIV_HBR, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) regmap_update_bits(hdptx->regmap, 0x016c, ROPLL_PMS_SDIV_HBR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) FIELD_PREP(ROPLL_PMS_SDIV_HBR2, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) regmap_update_bits(hdptx->regmap, 0x0178, ANA_ROPLL_SDM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) FIELD_PREP(ANA_ROPLL_SDM_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) regmap_update_bits(hdptx->regmap, 0x0178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) OVRD_ROPLL_SDM_RSTN | ROPLL_SDM_RSTN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) FIELD_PREP(OVRD_ROPLL_SDM_RSTN, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) FIELD_PREP(ROPLL_SDM_RSTN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_RBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_RBR, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR2, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) regmap_update_bits(hdptx->regmap, 0x017c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) OVRD_ROPLL_SDC_RSTN | ROPLL_SDC_RSTN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) FIELD_PREP(OVRD_ROPLL_SDC_RSTN, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) FIELD_PREP(ROPLL_SDC_RSTN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) regmap_write(hdptx->regmap, 0x0180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) regmap_write(hdptx->regmap, 0x0184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) regmap_write(hdptx->regmap, 0x0188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) regmap_update_bits(hdptx->regmap, 0x0190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ROPLL_SDM_NUMERATOR_SIGN_RBR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ROPLL_SDM_NUMERATOR_SIGN_HBR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ROPLL_SDM_NUMERATOR_SIGN_HBR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_RBR, 0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR2, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) regmap_write(hdptx->regmap, 0x0194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) FIELD_PREP(ROPLL_SDM_NUMERATOR, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) regmap_write(hdptx->regmap, 0x0198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) regmap_write(hdptx->regmap, 0x019c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) regmap_update_bits(hdptx->regmap, 0x01a4, ROPLL_SDC_N_RBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) FIELD_PREP(ROPLL_SDC_N_RBR, 0x2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) regmap_update_bits(hdptx->regmap, 0x01a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ROPLL_SDC_N_HBR | ROPLL_SDC_N_HBR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) FIELD_PREP(ROPLL_SDC_N_HBR, 0x2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) FIELD_PREP(ROPLL_SDC_N_HBR2, 0x2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) regmap_write(hdptx->regmap, 0x01b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) regmap_write(hdptx->regmap, 0x01b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) regmap_write(hdptx->regmap, 0x01b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) regmap_write(hdptx->regmap, 0x01c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) regmap_write(hdptx->regmap, 0x01c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) regmap_write(hdptx->regmap, 0x01c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) regmap_update_bits(hdptx->regmap, 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) OVRD_ROPLL_SDC_NDIV_RSTN | ROPLL_SDC_NDIV_RSTN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) FIELD_PREP(ROPLL_SDC_NDIV_RSTN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) regmap_update_bits(hdptx->regmap, 0x01dc, ANA_ROPLL_SSC_CLK_DIV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) regmap_update_bits(hdptx->regmap, 0x0118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ROPLL_ANA_CPP_CTRL_COARSE | ROPLL_ANA_CPP_CTRL_FINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE, 0xe) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE, 0xe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) regmap_update_bits(hdptx->regmap, 0x011c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ROPLL_ANA_LPF_C_SEL_COARSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ROPLL_ANA_LPF_C_SEL_FINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE, 0x4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE, 0x4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) regmap_update_bits(hdptx->regmap, 0x0204, ANA_PLL_CD_TX_SER_RATE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) regmap_update_bits(hdptx->regmap, 0x025c, DIG_CLK_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) FIELD_PREP(DIG_CLK_SEL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) regmap_update_bits(hdptx->regmap, 0x021c, ANA_PLL_TX_HS_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) FIELD_PREP(ANA_PLL_TX_HS_CLK_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) regmap_update_bits(hdptx->regmap, 0x0204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ANA_PLL_CD_HSCLK_EAST_EN | ANA_PLL_CD_HSCLK_WEST_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) regmap_update_bits(hdptx->regmap, 0x0264, CMN_ROPLL_ALONE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) FIELD_PREP(CMN_ROPLL_ALONE_MODE, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) regmap_update_bits(hdptx->regmap, 0x0208, ANA_PLL_CD_VREG_GAIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL, 0x4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) regmap_update_bits(hdptx->regmap, 0x00f0, ANA_LCPLL_RESERVED7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) FIELD_PREP(ANA_LCPLL_RESERVED7, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) regmap_update_bits(hdptx->regmap, 0x020c, ANA_PLL_CD_VREG_ICTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) FIELD_PREP(ANA_PLL_CD_VREG_ICTRL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) regmap_update_bits(hdptx->regmap, 0x0214, ANA_PLL_SYNC_LOSS_DET_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE, 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) regmap_update_bits(hdptx->regmap, 0x0210, PLL_LCRO_CLK_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) FIELD_PREP(PLL_LCRO_CLK_SEL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) regmap_update_bits(hdptx->regmap, 0x0268, HS_SPEED_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) FIELD_PREP(HS_SPEED_SEL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) regmap_update_bits(hdptx->regmap, 0x026c, LS_SPEED_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) FIELD_PREP(LS_SPEED_SEL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) regmap_update_bits(hdptx->regmap, 0x0414, ANA_SB_TX_HLVL_PROG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) FIELD_PREP(ANA_SB_TX_HLVL_PROG, 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) regmap_update_bits(hdptx->regmap, 0x0418, ANA_SB_TX_LLVL_PROG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) FIELD_PREP(ANA_SB_TX_LLVL_PROG, 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) regmap_update_bits(hdptx->regmap, 0x044c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) SB_RX_RCAL_OPT_CODE | SB_RX_RTERM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) FIELD_PREP(SB_RX_RCAL_OPT_CODE, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) FIELD_PREP(SB_RX_RTERM_CTRL, 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) regmap_update_bits(hdptx->regmap, 0x0450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) SB_TG_SB_EN_DELAY_TIME | SB_TG_RXTERN_EN_DELAY_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) FIELD_PREP(SB_TG_SB_EN_DELAY_TIME, 0x2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) FIELD_PREP(SB_TG_RXTERN_EN_DELAY_TIME, 0x2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) regmap_update_bits(hdptx->regmap, 0x0454,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) SB_READY_DELAY_TIME | SB_TG_OSC_EN_DELAY_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) FIELD_PREP(SB_READY_DELAY_TIME, 0x2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME, 0x2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) regmap_update_bits(hdptx->regmap, 0x0458,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) FIELD_PREP(SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 0x2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) regmap_update_bits(hdptx->regmap, 0x045c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) SB_TG_PLL_CD_VREG_FAST_PULSE_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) FIELD_PREP(SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 0x4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) regmap_update_bits(hdptx->regmap, 0x0460,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) SB_TG_EARC_DMRX_RECVRD_CLK_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 0xa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) regmap_update_bits(hdptx->regmap, 0x0468, SB_TG_CNT_RUN_NO_7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) FIELD_PREP(SB_TG_CNT_RUN_NO_7_0, 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) regmap_update_bits(hdptx->regmap, 0x046c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) SB_EARC_SIG_DET_BYPASS | SB_AFC_TOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) FIELD_PREP(SB_EARC_SIG_DET_BYPASS, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) FIELD_PREP(SB_AFC_TOL, 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) regmap_update_bits(hdptx->regmap, 0x0470, SB_AFC_STB_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) FIELD_PREP(SB_AFC_STB_NUM, 0x4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) regmap_update_bits(hdptx->regmap, 0x0474, SB_TG_OSC_CNT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) FIELD_PREP(SB_TG_OSC_CNT_MIN, 0x67));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) regmap_update_bits(hdptx->regmap, 0x0478, SB_TG_OSC_CNT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) FIELD_PREP(SB_TG_OSC_CNT_MAX, 0x6a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) regmap_update_bits(hdptx->regmap, 0x047c, SB_PWM_AFC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) FIELD_PREP(SB_PWM_AFC_CTRL, 0x5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) regmap_update_bits(hdptx->regmap, 0x0434, ANA_SB_DMRX_LPBK_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) FIELD_PREP(ANA_SB_DMRX_LPBK_DATA, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) regmap_update_bits(hdptx->regmap, 0x0440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ANA_SB_VREG_OUT_SEL | ANA_SB_VREG_REF_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) FIELD_PREP(ANA_SB_VREG_OUT_SEL, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) FIELD_PREP(ANA_SB_VREG_REF_SEL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) regmap_update_bits(hdptx->regmap, 0x043c, ANA_SB_VREG_GAIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) FIELD_PREP(ANA_SB_VREG_GAIN_CTRL, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) regmap_update_bits(hdptx->regmap, 0x0408, ANA_SB_RXTERM_OFFSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) FIELD_PREP(ANA_SB_RXTERM_OFFSP, 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) regmap_update_bits(hdptx->regmap, 0x040c, ANA_SB_RXTERM_OFFSN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) FIELD_PREP(ANA_SB_RXTERM_OFFSN, 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) regmap_update_bits(hdptx->regmap, 0x047c, SB_RCAL_RSTN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) FIELD_PREP(SB_RCAL_RSTN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) FIELD_PREP(SB_AUX_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) regmap_update_bits(hdptx->regmap, 0x0480, SB_AUX_EN_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) FIELD_PREP(SB_AUX_EN_IN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) regmap_update_bits(hdptx->regmap, 0x040c, OVRD_SB_RX_RESCAL_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) FIELD_PREP(OVRD_SB_RX_RESCAL_DONE, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) FIELD_PREP(OVRD_SB_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) regmap_update_bits(hdptx->regmap, 0x0408, OVRD_SB_RXTERM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) FIELD_PREP(OVRD_SB_RXTERM_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) regmap_update_bits(hdptx->regmap, 0x043c, OVRD_SB_VREG_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) FIELD_PREP(OVRD_SB_VREG_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_AUX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) FIELD_PREP(OVRD_SB_AUX_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) FIELD_PREP(BGR_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) FIELD_PREP(BIAS_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) reset_control_deassert(hdptx->init_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) reset_control_deassert(hdptx->cmn_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) regmap_update_bits(hdptx->regmap, 0x040c, SB_RX_RESCAL_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) FIELD_PREP(SB_RX_RESCAL_DONE, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) regmap_update_bits(hdptx->regmap, 0x0410, SB_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) FIELD_PREP(SB_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) regmap_update_bits(hdptx->regmap, 0x0408, SB_RXRERM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) FIELD_PREP(SB_RXRERM_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) regmap_update_bits(hdptx->regmap, 0x043c, SB_VREG_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) FIELD_PREP(SB_VREG_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) FIELD_PREP(SB_AUX_EN, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) status, FIELD_GET(SB_RDY, status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) 50, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) dev_err(hdptx->dev, "timeout waiting for sb_rdy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static void rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) u32 lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) reset_control_assert(hdptx->lane_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) reset_control_assert(hdptx->cmn_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) reset_control_assert(hdptx->init_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) reset_control_assert(hdptx->apb_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) reset_control_deassert(hdptx->apb_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) for (lane = 0; lane < 4; lane++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) OVRD_LN_TX_DRV_EI_EN | LN_TX_DRV_EI_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) FIELD_PREP(OVRD_LN_TX_DRV_EI_EN, 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) FIELD_PREP(LN_TX_DRV_EI_EN, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) FIELD_PREP(PLL_EN, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) FIELD_PREP(BIAS_EN, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) FIELD_PREP(BGR_EN, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static bool rockchip_hdptx_phy_enabled(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) regmap_read(hdptx->grf, HDPTXPHY_GRF_STATUS0, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return FIELD_GET(SB_RDY, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int rockchip_hdptx_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) enum phy_mode mode = phy_get_mode(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) u32 lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (rockchip_hdptx_phy_enabled(hdptx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) rockchip_hdptx_phy_reset(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) for (lane = 0; lane < 4; lane++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) u32 invert = hdptx->lane_polarity_invert[lane];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) LN_POLARITY_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) FIELD_PREP(LN_POLARITY_INV, invert));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (mode == PHY_MODE_DP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) HDPTX_MODE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) FIELD_PREP(HDPTX_MODE_SEL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) FIELD_PREP(PROTOCOL_SEL, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) regmap_update_bits(hdptx->regmap, 0x0818, DATA_BUS_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) FIELD_PREP(DATA_BUS_WIDTH, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) regmap_update_bits(hdptx->regmap, 0x0818, BUS_WIDTH_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) FIELD_PREP(BUS_WIDTH_SEL, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) rockchip_hdptx_phy_dp_pll_init(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) rockchip_hdptx_phy_dp_aux_init(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) HDPTX_MODE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) FIELD_PREP(HDPTX_MODE_SEL, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) FIELD_PREP(PROTOCOL_SEL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int rockchip_hdptx_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) rockchip_hdptx_phy_reset(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static const struct phy_ops rockchip_hdptx_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .set_mode = rockchip_hdptx_phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .configure = rockchip_hdptx_phy_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .power_on = rockchip_hdptx_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .power_off = rockchip_hdptx_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static bool rockchip_hdptx_phy_is_accissible_reg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) case 0x0000 ... 0x029c: /* CMN Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) case 0x0400 ... 0x04a4: /* Sideband Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) case 0x0800 ... 0x08a4: /* Lane Top Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) case 0x0c00 ... 0x0cb4: /* Lane 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) case 0x1000 ... 0x10b4: /* Lane 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) case 0x1400 ... 0x14b4: /* Lane 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) case 0x1800 ... 0x18b4: /* Lane 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static const struct regmap_config rockchip_hdptx_phy_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .max_register = 0x18b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .readable_reg = rockchip_hdptx_phy_is_accissible_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .writeable_reg = rockchip_hdptx_phy_is_accissible_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static int rockchip_hdptx_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct rockchip_hdptx_phy *hdptx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (!hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) hdptx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) platform_set_drvdata(pdev, hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) hdptx->regmap = devm_regmap_init_mmio(dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) &rockchip_hdptx_phy_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (IS_ERR(hdptx->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return dev_err_probe(dev, PTR_ERR(hdptx->regmap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) "failed to create regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = devm_clk_bulk_get_all(dev, &hdptx->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (ret < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return dev_err_probe(dev, ret, "failed to get clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) hdptx->nr_clks = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) hdptx->apb_reset = devm_reset_control_get(dev, "apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (IS_ERR(hdptx->apb_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return dev_err_probe(dev, PTR_ERR(hdptx->apb_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) "failed to get apb reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) hdptx->init_reset = devm_reset_control_get(dev, "init");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (IS_ERR(hdptx->init_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return dev_err_probe(dev, PTR_ERR(hdptx->init_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) "failed to get init reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) hdptx->cmn_reset = devm_reset_control_get(dev, "cmn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (IS_ERR(hdptx->cmn_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return dev_err_probe(dev, PTR_ERR(hdptx->cmn_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) "failed to get cmn reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) hdptx->lane_reset = devm_reset_control_get(dev, "lane");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (IS_ERR(hdptx->lane_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return dev_err_probe(dev, PTR_ERR(hdptx->lane_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) "failed to get lane reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (IS_ERR(hdptx->grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return dev_err_probe(dev, PTR_ERR(hdptx->grf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) "failed to get grf regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) device_property_read_u32_array(dev, "lane-polarity-invert",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) hdptx->lane_polarity_invert, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ret = rockchip_hdptx_phy_parse_training_table(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return dev_err_probe(dev, ret, "failed to parse training table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) phy = devm_phy_create(dev, NULL, &rockchip_hdptx_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (IS_ERR(phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return dev_err_probe(dev, PTR_ERR(phy), "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) phy_set_drvdata(phy, hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static const struct of_device_id rockchip_hdptx_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) { .compatible = "rockchip,rk3588-hdptx-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) MODULE_DEVICE_TABLE(of, rockchip_hdptx_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static struct platform_driver rockchip_hdptx_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .probe = rockchip_hdptx_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .name = "rockchip-hdptx-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .of_match_table = rockchip_hdptx_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) module_platform_driver(rockchip_hdptx_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) MODULE_DESCRIPTION("Rockchip HDMI/DP Combo PHY with Samsung IP block");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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