^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) Rockchip Electronics Co.Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Algea Cao <algea.cao@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rational.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rockchip/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GRF_HDPTX_CON0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HDPTX_I_PLL_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HDPTX_I_BIAS_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HDPTX_I_BGR_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GRF_HDPTX_STATUS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HDPTX_O_PLL_LOCK_DONE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HDPTX_O_PHY_CLK_RDY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HDPTX_O_PHY_RDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HDPTX_O_SB_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CMN_REG0000 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CMN_REG0001 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CMN_REG0002 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CMN_REG0003 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CMN_REG0004 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CMN_REG0005 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CMN_REG0006 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CMN_REG0007 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CMN_REG0008 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LCPLL_EN_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LCPLL_EN(x) UPDATE(x, 4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LCPLL_LCVCO_MODE_EN_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LCPLL_LCVCO_MODE_EN(x) UPDATE(x, 4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CMN_REG0009 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CMN_REG000A 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CMN_REG000B 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CMN_REG000C 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CMN_REG000D 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CMN_REG000E 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CMN_REG000F 0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CMN_REG0010 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CMN_REG0011 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CMN_REG0012 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CMN_REG0013 0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CMN_REG0014 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CMN_REG0015 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CMN_REG0016 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CMN_REG0017 0x005C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CMN_REG0018 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CMN_REG0019 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CMN_REG001A 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CMN_REG001B 0x006C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CMN_REG001C 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CMN_REG001D 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CMN_REG001E 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LCPLL_PI_EN_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LCPLL_PI_EN(x) UPDATE(x, 5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LCPLL_100M_CLK_EN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LCPLL_100M_CLK_EN(x) UPDATE(x, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CMN_REG001F 0x007C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CMN_REG0020 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CMN_REG0021 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CMN_REG0022 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CMN_REG0023 0x008C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CMN_REG0024 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CMN_REG0025 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LCPLL_PMS_IQDIV_RSTN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CMN_REG0026 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CMN_REG0027 0x009C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CMN_REG0028 0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LCPLL_SDC_FRAC_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LCPLL_SDC_FRAC_RSTN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CMN_REG0029 0x00A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CMN_REG002A 0x00A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CMN_REG002B 0x00AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CMN_REG002C 0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CMN_REG002D 0x00B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LCPLL_SDC_N_MASK GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LCPLL_SDC_N(x) UPDATE(x, 3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CMN_REG002E 0x00B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LCPLL_SDC_NUMBERATOR(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CMN_REG002F 0x00BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LCPLL_SDC_DENOMINATOR(x) UPDATE(x, 7, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LCPLL_SDC_NDIV_RSTN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CMN_REG0030 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CMN_REG0031 0x00C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CMN_REG0032 0x00C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CMN_REG0033 0x00CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CMN_REG0034 0x00D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CMN_REG0035 0x00D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CMN_REG0036 0x00D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CMN_REG0037 0x00DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CMN_REG0038 0x00E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CMN_REG0039 0x00E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CMN_REG003A 0x00E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CMN_REG003B 0x00EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CMN_REG003C 0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CMN_REG003D 0x00F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ROPLL_LCVCO_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CMN_REG003E 0x00F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CMN_REG003F 0x00FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CMN_REG0040 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CMN_REG0041 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CMN_REG0042 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CMN_REG0043 0x010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CMN_REG0044 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CMN_REG0045 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CMN_REG0046 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CMN_REG0047 0x011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CMN_REG0048 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CMN_REG0049 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CMN_REG004A 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CMN_REG004B 0x012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CMN_REG004C 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CMN_REG004D 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CMN_REG004E 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ROPLL_PI_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CMN_REG004F 0x013C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CMN_REG0050 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CMN_REG0051 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CMN_REG0052 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CMN_REG0053 0x014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CMN_REG0054 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CMN_REG0055 0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CMN_REG0056 0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CMN_REG0057 0x015C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CMN_REG0058 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CMN_REG0059 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CMN_REG005A 0x0168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CMN_REG005B 0x016C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CMN_REG005C 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ROPLL_PMS_IQDIV_RSTN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CMN_REG005D 0x0174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CMN_REG005E 0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ROPLL_SDM_EN_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ROPLL_SDM_EN(x) UPDATE(x, 6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ROPLL_SDM_FRAC_EN_RBR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ROPLL_SDM_FRAC_EN_HBR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ROPLL_SDM_FRAC_EN_HBR2 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ROPLL_SDM_FRAC_EN_HBR3 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CMN_REG005F 0x017C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CMN_REG0060 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CMN_REG0061 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CMN_REG0062 0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CMN_REG0063 0x018C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CMN_REG0064 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ROPLL_SDM_NUM_SIGN_RBR(x) UPDATE(x, 3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CMN_REG0065 0x0194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CMN_REG0066 0x0198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CMN_REG0067 0x019C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CMN_REG0068 0x01A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CMN_REG0069 0x01A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ROPLL_SDC_N_RBR(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CMN_REG006A 0x01A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CMN_REG006B 0x01AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CMN_REG006C 0x01B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CMN_REG006D 0x01B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CMN_REG006E 0x01B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CMN_REG006F 0x01BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CMN_REG0070 0x01C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CMN_REG0071 0x01C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CMN_REG0072 0x01C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CMN_REG0073 0x01CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CMN_REG0074 0x01D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ROPLL_SDC_NDIV_RSTN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ROPLL_SSC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CMN_REG0075 0x01D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CMN_REG0076 0x01D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CMN_REG0077 0x01DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CMN_REG0078 0x01E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CMN_REG0079 0x01E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CMN_REG007A 0x01E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CMN_REG007B 0x01EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CMN_REG007C 0x01F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CMN_REG007D 0x01F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CMN_REG007E 0x01F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CMN_REG007F 0x01FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CMN_REG0080 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CMN_REG0081 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OVRD_PLL_CD_CLK_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PLL_CD_HSCLK_EAST_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CMN_REG0082 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CMN_REG0083 0x020C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CMN_REG0084 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CMN_REG0085 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CMN_REG0086 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PLL_PCG_POSTDIV_SEL(x) UPDATE(x, 7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PLL_PCG_CLK_SEL(x) UPDATE(x, 3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PLL_PCG_CLK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CMN_REG0087 0x021C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PLL_FRL_MODE_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PLL_TX_HS_CLK_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CMN_REG0088 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CMN_REG0089 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define LCPLL_ALONE_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CMN_REG008A 0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CMN_REG008B 0x022C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CMN_REG008C 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CMN_REG008D 0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CMN_REG008E 0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CMN_REG008F 0x023C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CMN_REG0090 0x0240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CMN_REG0091 0x0244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CMN_REG0092 0x0248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CMN_REG0093 0x024C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CMN_REG0094 0x0250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CMN_REG0095 0x0254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CMN_REG0096 0x0258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CMN_REG0097 0x025C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DIG_CLK_SEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ROPLL_REF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define LCPLL_REF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CMN_REG0098 0x0260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CMN_REG0099 0x0264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CMN_ROPLL_ALONE_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define ROPLL_ALONE_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CMN_REG009A 0x0268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define HS_SPEED_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define DIV_10_CLOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CMN_REG009B 0x026C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IS_SPEED_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define LINK_SYMBOL_CLOCK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define LINK_SYMBOL_CLOCK1_2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CMN_REG009C 0x0270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CMN_REG009D 0x0274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CMN_REG009E 0x0278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CMN_REG009F 0x027C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CMN_REG00A0 0x0280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CMN_REG00A1 0x0284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CMN_REG00A2 0x0288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CMN_REG00A3 0x028C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CMN_REG00AD 0x0290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CMN_REG00A5 0x0294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CMN_REG00A6 0x0298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CMN_REG00A7 0x029C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SB_REG0100 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SB_REG0101 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SB_REG0102 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define OVRD_SB_RXTERM_EN_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define OVRD_SB_RXTERM_EN(x) UPDATE(x, 5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SB_RXTERM_EN_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SB_RXTERM_EN(x) UPDATE(x, 4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ANA_SB_RXTERM_OFFSP(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SB_REG0103 0x040C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ANA_SB_RXTERM_OFFSN(x) UPDATE(x, 6, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OVRD_SB_RX_RESCAL_DONE(x) UPDATE(x, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SB_RX_RESCAL_DONE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SB_RX_RESCAL_DONE(x) UPDATE(x, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SB_REG0104 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define OVRD_SB_EN_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define OVRD_SB_EN(x) UPDATE(x, 5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SB_EN_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SB_EN(x) UPDATE(x, 4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SB_REG0105 0x0414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define OVRD_SB_EARC_CMDC_EN_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define OVRD_SB_EARC_CMDC_EN(x) UPDATE(x, 6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SB_EARC_CMDC_EN_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SB_EARC_CMDC_EN(x) UPDATE(x, 5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ANA_SB_TX_HLVL_PROG(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SB_REG0106 0x0418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ANA_SB_TX_LLVL_PROG(x) UPDATE(x, 6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SB_REG0107 0x041C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SB_REG0108 0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SB_REG0109 0x0424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ANA_SB_DMRX_AFC_DIV_RATIO(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SB_REG010A 0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SB_REG010B 0x042C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SB_REG010C 0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SB_REG010D 0x0434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SB_REG010E 0x0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SB_REG010F 0x043C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define OVRD_SB_VREG_EN_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define OVRD_SB_VREG_EN(x) UPDATE(x, 7, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SB_VREG_EN_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SB_VREG_EN(x) UPDATE(x, 6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define OVRD_SB_VREG_LPF_BYPASS(x) UPDATE(x, 5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SB_VREG_LPF_BYPASS_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SB_VREG_LPF_BYPASS(x) UPDATE(x, 4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ANA_SB_VREG_GAIN_CTRL(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SB_REG0110 0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ANA_SB_VREG_REF_SEL_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ANA_SB_VREG_REF_SEL(x) UPDATE(x, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SB_REG0111 0x0444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SB_REG0112 0x0448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SB_REG0113 0x044C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SB_RX_RCAL_OPT_CODE(x) UPDATE(x, 5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SB_RX_RTERM_CTRL(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SB_REG0114 0x0450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SB_TG_SB_EN_DELAY_TIME(x) UPDATE(x, 5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SB_TG_RXTERM_EN_DELAY_TIME(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SB_REG0115 0x0454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SB_READY_DELAY_TIME_MASK GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SB_READY_DELAY_TIME(x) UPDATE(x, 5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SB_TG_OSC_EN_DELAY_TIME(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SB_REG0116 0x0458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define AFC_RSTN_DELAY_TIME(x) UPDATE(x, 6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SB_REG0117 0x045C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define FAST_PULSE_TIME_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define FAST_PULSE_TIME(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SB_REG0118 0x0460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SB_REG0119 0x0464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SB_REG011A 0x0468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SB_REG011B 0x046C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SB_EARC_SIG_DET_BYPASS_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SB_EARC_SIG_DET_BYPASS(x) UPDATE(x, 4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SB_AFC_TOL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SB_AFC_TOL(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SB_REG011C 0x0470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SB_REG011D 0x0474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SB_REG011E 0x0478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SB_REG011F 0x047C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SB_PWM_AFC_CTRL(x) UPDATE(x, 7, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SB_RCAL_RSTN_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SB_RCAL_RSTN(x) UPDATE(x, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SB_REG0120 0x0480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SB_EARC_EN_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SB_EARC_EN(x) UPDATE(x, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SB_EARC_AFC_EN_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SB_EARC_AFC_EN(x) UPDATE(x, 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SB_REG0121 0x0484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SB_REG0122 0x0488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SB_REG0123 0x048C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define OVRD_SB_READY_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define OVRD_SB_READY(x) UPDATE(x, 5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SB_READY_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SB_READY(x) UPDATE(x, 4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SB_REG0124 0x0490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SB_REG0125 0x0494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SB_REG0126 0x0498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SB_REG0127 0x049C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SB_REG0128 0x04A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SB_REG0129 0x04AD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define LNTOP_REG0200 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PROTOCOL_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define HDMI_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define HDMI_TMDS_FRL_SEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define LNTOP_REG0201 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define LNTOP_REG0202 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define LNTOP_REG0203 0x080C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define LNTOP_REG0204 0x0810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define LNTOP_REG0205 0x0814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define LNTOP_REG0206 0x0818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define DATA_BUS_WIDTH (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define WIDTH_40BIT (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define WIDTH_36BIT (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define DATA_BUS_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define DATA_BUS_36_40 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define LNTOP_REG0207 0x081C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define LANE_EN 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define ALL_LANE_EN 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define LNTOP_REG0208 0x0820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define LNTOP_REG0209 0x0824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define LNTOP_REG020A 0x0828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define LNTOP_REG020B 0x082C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define LNTOP_REG020C 0x0830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define LNTOP_REG020D 0x0834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define LNTOP_REG020E 0x0838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define LNTOP_REG020F 0x083C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define LNTOP_REG0210 0x0840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define LNTOP_REG0211 0x0844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define LNTOP_REG0212 0x0848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define LNTOP_REG0213 0x084C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define LNTOP_REG0214 0x0850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define LNTOP_REG0215 0x0854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define LNTOP_REG0216 0x0858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define LNTOP_REG0217 0x085C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define LNTOP_REG0218 0x0860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define LNTOP_REG0219 0x0864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define LNTOP_REG021A 0x0868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define LNTOP_REG021B 0x086C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define LNTOP_REG021C 0x0870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define LNTOP_REG021D 0x0874
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define LNTOP_REG021E 0x0878
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define LNTOP_REG021F 0x087C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define LNTOP_REG0220 0x0880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define LNTOP_REG0221 0x0884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define LNTOP_REG0222 0x0888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define LNTOP_REG0223 0x088C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define LNTOP_REG0224 0x0890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define LNTOP_REG0225 0x0894
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define LNTOP_REG0226 0x0898
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define LNTOP_REG0227 0x089C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define LNTOP_REG0228 0x08A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define LNTOP_REG0229 0x08A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define LANE_REG0300 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define LANE_REG0301 0x0C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define LANE_REG0302 0x0C08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define LANE_REG0303 0x0C0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define LANE_REG0304 0x0C10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define LANE_REG0305 0x0C14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define LANE_REG0306 0x0C18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define LANE_REG0307 0x0C1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define LANE_REG0308 0x0C20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define LANE_REG0309 0x0C24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define LANE_REG030A 0x0C28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define LANE_REG030B 0x0C2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define LANE_REG030C 0x0C30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define LANE_REG030D 0x0C34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define LANE_REG030E 0x0C38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define LANE_REG030F 0x0C3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define LANE_REG0310 0x0C40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define LANE_REG0311 0x0C44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define LANE_REG0312 0x0C48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define LN0_TX_SER_RATE_SEL_RBR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define LN0_TX_SER_RATE_SEL_HBR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define LN0_TX_SER_RATE_SEL_HBR2 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define LN0_TX_SER_RATE_SEL_HBR3 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define LANE_REG0313 0x0C4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define LANE_REG0314 0x0C50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define LANE_REG0315 0x0C54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define LANE_REG0316 0x0C58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define LANE_REG0317 0x0C5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define LANE_REG0318 0x0C60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define LANE_REG0319 0x0C64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define LANE_REG031A 0x0C68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define LANE_REG031B 0x0C6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define LANE_REG031C 0x0C70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define LANE_REG031D 0x0C74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define LANE_REG031E 0x0C78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define LANE_REG031F 0x0C7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define LANE_REG0320 0x0C80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define LANE_REG0321 0x0C84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define LANE_REG0322 0x0C88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define LANE_REG0323 0x0C8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define LANE_REG0324 0x0C90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define LANE_REG0325 0x0C94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define LANE_REG0326 0x0C98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define LANE_REG0327 0x0C9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define LANE_REG0328 0x0CA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define LANE_REG0329 0x0CA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define LANE_REG032A 0x0CA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define LANE_REG032B 0x0CAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define LANE_REG032C 0x0CB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define LANE_REG032D 0x0CB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define LANE_REG0400 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define LANE_REG0401 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define LANE_REG0402 0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define LANE_REG0403 0x100C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define LANE_REG0404 0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define LANE_REG0405 0x1014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define LANE_REG0406 0x1018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define LANE_REG0407 0x101C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define LANE_REG0408 0x1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define LANE_REG0409 0x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define LANE_REG040A 0x1028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define LANE_REG040B 0x102C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define LANE_REG040C 0x1030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define LANE_REG040D 0x1034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define LANE_REG040E 0x1038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define LANE_REG040F 0x103C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define LANE_REG0410 0x1040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define LANE_REG0411 0x1044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define LANE_REG0412 0x1048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define LN1_TX_SER_RATE_SEL_RBR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define LN1_TX_SER_RATE_SEL_HBR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define LN1_TX_SER_RATE_SEL_HBR2 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define LN1_TX_SER_RATE_SEL_HBR3 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define LANE_REG0413 0x104C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define LANE_REG0414 0x1050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define LANE_REG0415 0x1054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define LANE_REG0416 0x1058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define LANE_REG0417 0x105C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define LANE_REG0418 0x1060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define LANE_REG0419 0x1064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define LANE_REG041A 0x1068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define LANE_REG041B 0x106C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define LANE_REG041C 0x1070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define LANE_REG041D 0x1074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define LANE_REG041E 0x1078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define LANE_REG041F 0x107C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define LANE_REG0420 0x1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define LANE_REG0421 0x1084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define LANE_REG0422 0x1088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define LANE_REG0423 0x108C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define LANE_REG0424 0x1090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define LANE_REG0425 0x1094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define LANE_REG0426 0x1098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define LANE_REG0427 0x109C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define LANE_REG0428 0x10A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define LANE_REG0429 0x10A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define LANE_REG042A 0x10A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define LANE_REG042B 0x10AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define LANE_REG042C 0x10B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define LANE_REG042D 0x10B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define LANE_REG0500 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define LANE_REG0501 0x1404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define LANE_REG0502 0x1408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define LANE_REG0503 0x140C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define LANE_REG0504 0x1410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define LANE_REG0505 0x1414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define LANE_REG0506 0x1418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define LANE_REG0507 0x141C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define LANE_REG0508 0x1420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define LANE_REG0509 0x1424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define LANE_REG050A 0x1428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define LANE_REG050B 0x142C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define LANE_REG050C 0x1430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define LANE_REG050D 0x1434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define LANE_REG050E 0x1438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define LANE_REG050F 0x143C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define LANE_REG0510 0x1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define LANE_REG0511 0x1444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define LANE_REG0512 0x1448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define LN2_TX_SER_RATE_SEL_RBR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define LN2_TX_SER_RATE_SEL_HBR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define LN2_TX_SER_RATE_SEL_HBR2 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define LN2_TX_SER_RATE_SEL_HBR3 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define LANE_REG0513 0x144C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define LANE_REG0514 0x1450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define LANE_REG0515 0x1454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define LANE_REG0516 0x1458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define LANE_REG0517 0x145C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define LANE_REG0518 0x1460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define LANE_REG0519 0x1464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define LANE_REG051A 0x1468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define LANE_REG051B 0x146C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define LANE_REG051C 0x1470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define LANE_REG051D 0x1474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define LANE_REG051E 0x1478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define LANE_REG051F 0x147C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define LANE_REG0520 0x1480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define LANE_REG0521 0x1484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define LANE_REG0522 0x1488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define LANE_REG0523 0x148C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define LANE_REG0524 0x1490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define LANE_REG0525 0x1494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define LANE_REG0526 0x1498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define LANE_REG0527 0x149C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define LANE_REG0528 0x14A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define LANE_REG0529 0x14AD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define LANE_REG052A 0x14A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define LANE_REG052B 0x14AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define LANE_REG052C 0x14B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define LANE_REG052D 0x14B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define LANE_REG0600 0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define LANE_REG0601 0x1804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define LANE_REG0602 0x1808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define LANE_REG0603 0x180C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define LANE_REG0604 0x1810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define LANE_REG0605 0x1814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define LANE_REG0606 0x1818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define LANE_REG0607 0x181C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define LANE_REG0608 0x1820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define LANE_REG0609 0x1824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define LANE_REG060A 0x1828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define LANE_REG060B 0x182C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define LANE_REG060C 0x1830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define LANE_REG060D 0x1834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define LANE_REG060E 0x1838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define LANE_REG060F 0x183C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define LANE_REG0610 0x1840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define LANE_REG0611 0x1844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define LANE_REG0612 0x1848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define LN3_TX_SER_RATE_SEL_RBR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define LN3_TX_SER_RATE_SEL_HBR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define LN3_TX_SER_RATE_SEL_HBR2 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define LN3_TX_SER_RATE_SEL_HBR3 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define LANE_REG0613 0x184C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define LANE_REG0614 0x1850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define LANE_REG0615 0x1854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define LANE_REG0616 0x1858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define LANE_REG0617 0x185C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define LANE_REG0618 0x1860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define LANE_REG0619 0x1864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define LANE_REG061A 0x1868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define LANE_REG061B 0x186C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define LANE_REG061C 0x1870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define LANE_REG061D 0x1874
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define LANE_REG061E 0x1878
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define LANE_REG061F 0x187C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define LANE_REG0620 0x1880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define LANE_REG0621 0x1884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define LANE_REG0622 0x1888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define LANE_REG0623 0x188C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define LANE_REG0624 0x1890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define LANE_REG0625 0x1894
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define LANE_REG0626 0x1898
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define LANE_REG0627 0x189C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define LANE_REG0628 0x18A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define LANE_REG0629 0x18A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define LANE_REG062A 0x18A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define LANE_REG062B 0x18AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define LANE_REG062C 0x18B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define LANE_REG062D 0x18B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define HDMI20_MAX_RATE 600000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define DATA_RATE_MASK 0xFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define COLOR_DEPTH_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define HDMI_MODE_MASK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define HDMI_EARC_MASK BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) enum hdptx_combphy_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) SS_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) SS_DP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct lcpll_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 bit_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u8 lcvco_mode_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u8 pi_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 clk_en_100m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u8 pms_mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u8 pms_mdiv_afc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u8 pms_pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u8 pms_refdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u8 pms_sdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u8 pi_cdiv_rstn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u8 pi_cdiv_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u8 sdm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u8 sdm_rstn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u8 sdc_frac_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u8 sdc_rstn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u8 sdm_deno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u8 sdm_num_sign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u8 sdm_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u8 sdc_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u8 sdc_n2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u8 sdc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u8 sdc_deno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u8 sdc_ndiv_rstn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u8 ssc_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u8 ssc_fm_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u8 ssc_fm_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u8 ssc_clk_div_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u8 cd_tx_ser_rate_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct ropll_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u32 bit_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u8 pms_mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u8 pms_mdiv_afc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u8 pms_pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u8 pms_refdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u8 pms_sdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8 pms_iqdiv_rstn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u8 ref_clk_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u8 sdm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u8 sdm_rstn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u8 sdc_frac_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u8 sdc_rstn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u8 sdm_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u8 sdm_deno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u8 sdm_num_sign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u8 sdm_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u8 sdc_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u8 sdc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u8 sdc_deno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u8 sdc_ndiv_rstn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u8 ssc_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u8 ssc_fm_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u8 ssc_fm_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u8 ssc_clk_div_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u8 ana_cpp_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u8 ana_lpf_c_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u8 cd_tx_ser_rate_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct rockchip_hdptx_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int nr_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct phy_config *phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* clk provider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct clk *dclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct reset_control *phy_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct reset_control *apb_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct reset_control *cmn_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct reset_control *init_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct reset_control *lane_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct reset_control *ropll_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct reset_control *lcpll_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) bool earc_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct lcpll_config lcpll_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) { 48000000, 1, 0, 0, 0x7d, 0x7d, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { 40000000, 1, 1, 0, 0x68, 0x68, 1, 1, 0, 0, 0, 1, 1, 1, 1, 9, 0, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 0, 2, 3, 1, 0, 0x20, 0x0c, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { 32000000, 1, 1, 1, 0x6b, 0x6b, 1, 1, 0, 1, 2, 1, 1, 1, 1, 9, 1, 2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 0, 0x0d, 0x18, 1, 0, 0x20, 0x0c, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) { ~0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct ropll_config ropll_frl_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) { 24000000, 0x19, 0x19, 1, 1, 0, 1, 2, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) { 18000000, 0x7d, 0x7d, 1, 1, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { 9000000, 0x7d, 0x7d, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) { ~0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct ropll_config ropll_tmds_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { ~0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static bool rockchip_hdptx_phy_is_accissible_reg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case 0x0000 ... 0x029c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case 0x0400 ... 0x04a4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case 0x0800 ... 0x08a4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case 0x0c00 ... 0x0cb4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case 0x1000 ... 0x10b4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case 0x1400 ... 0x14b4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case 0x1800 ... 0x18b4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static const struct regmap_config rockchip_hdptx_phy_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .max_register = 0x18b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .name = "hdptx-combphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .readable_reg = rockchip_hdptx_phy_is_accissible_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .writeable_reg = rockchip_hdptx_phy_is_accissible_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static inline struct rockchip_hdptx_phy *to_rockchip_hdptx_phy(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return container_of(hw, struct rockchip_hdptx_phy, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static inline void hdptx_write(struct rockchip_hdptx_phy *hdptx, u32 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) regmap_write(hdptx->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static inline u8 hdptx_read(struct rockchip_hdptx_phy *hdptx, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) regmap_read(hdptx->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static inline void hdptx_update_bits(struct rockchip_hdptx_phy *hdptx, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) regmap_update_bits(hdptx->regmap, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static inline void hdptx_grf_write(struct rockchip_hdptx_phy *hdptx, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) regmap_write(hdptx->grf, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static inline u8 hdptx_grf_read(struct rockchip_hdptx_phy *hdptx, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) regmap_read(hdptx->grf, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static void hdptx_pre_power_up(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) reset_control_assert(hdptx->apb_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) reset_control_deassert(hdptx->apb_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) reset_control_assert(hdptx->lane_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) reset_control_assert(hdptx->cmn_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) reset_control_assert(hdptx->init_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int hdptx_post_enable_lane(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) reset_control_deassert(hdptx->lane_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | HDPTX_I_BIAS_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) HDPTX_I_BGR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) hdptx_write(hdptx, LNTOP_REG0207, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) for (i = 0; i < 50; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) val = hdptx_grf_read(hdptx, GRF_HDPTX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (val & HDPTX_O_PHY_RDY && val & HDPTX_O_PLL_LOCK_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (i == 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) dev_err(hdptx->dev, "hdptx phy lane can't ready!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_err(hdptx->dev, "hdptx phy lane locked!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int hdptx_post_enable_pll(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | HDPTX_I_BIAS_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) HDPTX_I_BGR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) reset_control_deassert(hdptx->init_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) reset_control_deassert(hdptx->cmn_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) for (i = 0; i < 20; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) val = hdptx_grf_read(hdptx, GRF_HDPTX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (val & HDPTX_O_PHY_CLK_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (i == 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) dev_err(hdptx->dev, "hdptx phy pll can't lock!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev_err(hdptx->dev, "hdptx phy pll locked!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static int hdptx_post_power_up(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | HDPTX_I_BIAS_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) HDPTX_I_BGR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) reset_control_deassert(hdptx->init_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) reset_control_deassert(hdptx->cmn_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) for (i = 0; i < 20; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) val = hdptx_grf_read(hdptx, GRF_HDPTX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (val & HDPTX_O_PLL_LOCK_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (i == 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev_err(hdptx->dev, "hdptx phy can't lock!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) reset_control_deassert(hdptx->lane_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) for (i = 0; i < 50; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) val = hdptx_grf_read(hdptx, GRF_HDPTX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (val & HDPTX_O_PHY_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (i == 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) dev_err(hdptx->dev, "hdptx phy can't ready!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dev_err(hdptx->dev, "hdptx phy locked!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static void hdptx_phy_disable(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* reset phy and apb, or phy locked flag may keep 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) reset_control_assert(hdptx->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) reset_control_deassert(hdptx->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) reset_control_assert(hdptx->apb_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) reset_control_deassert(hdptx->apb_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) hdptx_write(hdptx, LANE_REG0300, 0x82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) hdptx_write(hdptx, SB_REG010F, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) hdptx_write(hdptx, SB_REG0110, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) hdptx_write(hdptx, LANE_REG0301, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) hdptx_write(hdptx, LANE_REG0401, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) hdptx_write(hdptx, LANE_REG0501, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) hdptx_write(hdptx, LANE_REG0601, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) reset_control_assert(hdptx->lane_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) reset_control_assert(hdptx->cmn_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) reset_control_assert(hdptx->init_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static void hdptx_earc_config(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) hdptx_update_bits(hdptx, SB_REG0113, SB_RX_RCAL_OPT_CODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) SB_RX_RCAL_OPT_CODE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) hdptx_write(hdptx, SB_REG011C, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) hdptx_update_bits(hdptx, SB_REG011B, SB_AFC_TOL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) SB_AFC_TOL(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) hdptx_write(hdptx, SB_REG0109, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) hdptx_update_bits(hdptx, SB_REG0120, SB_EARC_EN_MASK | SB_EARC_AFC_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) SB_EARC_EN(1) | SB_EARC_AFC_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) hdptx_update_bits(hdptx, SB_REG011B, SB_EARC_SIG_DET_BYPASS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) SB_EARC_SIG_DET_BYPASS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) hdptx_update_bits(hdptx, SB_REG011F, SB_PWM_AFC_CTRL_MASK | SB_RCAL_RSTN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) SB_PWM_AFC_CTRL(0xc) | SB_RCAL_RSTN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) hdptx_update_bits(hdptx, SB_REG0115, SB_READY_DELAY_TIME_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) SB_READY_DELAY_TIME(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) hdptx_update_bits(hdptx, SB_REG0113, SB_RX_RTERM_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) SB_RX_RTERM_CTRL(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) hdptx_update_bits(hdptx, SB_REG0102, ANA_SB_RXTERM_OFFSP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ANA_SB_RXTERM_OFFSP(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) hdptx_update_bits(hdptx, SB_REG0103, ANA_SB_RXTERM_OFFSN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ANA_SB_RXTERM_OFFSN(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) hdptx_write(hdptx, SB_REG011A, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) hdptx_write(hdptx, SB_REG0118, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) hdptx_write(hdptx, SB_REG011E, 0x6a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) hdptx_write(hdptx, SB_REG011D, 0x67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) hdptx_update_bits(hdptx, SB_REG0117, FAST_PULSE_TIME_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) FAST_PULSE_TIME(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) hdptx_update_bits(hdptx, SB_REG0114, SB_TG_SB_EN_DELAY_TIME_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) SB_TG_RXTERM_EN_DELAY_TIME_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) SB_TG_SB_EN_DELAY_TIME(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) SB_TG_RXTERM_EN_DELAY_TIME(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) hdptx_update_bits(hdptx, SB_REG0105, ANA_SB_TX_HLVL_PROG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ANA_SB_TX_HLVL_PROG(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) hdptx_update_bits(hdptx, SB_REG0106, ANA_SB_TX_LLVL_PROG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ANA_SB_TX_LLVL_PROG(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) hdptx_update_bits(hdptx, SB_REG010F, ANA_SB_VREG_GAIN_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ANA_SB_VREG_GAIN_CTRL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) hdptx_update_bits(hdptx, SB_REG0110, ANA_SB_VREG_REF_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ANA_SB_VREG_REF_SEL(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) hdptx_update_bits(hdptx, SB_REG0115, SB_TG_OSC_EN_DELAY_TIME_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) SB_TG_OSC_EN_DELAY_TIME(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) hdptx_update_bits(hdptx, SB_REG0116, AFC_RSTN_DELAY_TIME_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) AFC_RSTN_DELAY_TIME(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) hdptx_update_bits(hdptx, SB_REG0109, ANA_SB_DMRX_AFC_DIV_RATIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ANA_SB_DMRX_AFC_DIV_RATIO(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) hdptx_update_bits(hdptx, SB_REG0103, OVRD_SB_RX_RESCAL_DONE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) OVRD_SB_RX_RESCAL_DONE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) hdptx_update_bits(hdptx, SB_REG0104, OVRD_SB_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) OVRD_SB_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) hdptx_update_bits(hdptx, SB_REG0102, OVRD_SB_RXTERM_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) OVRD_SB_RXTERM_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) hdptx_update_bits(hdptx, SB_REG0105, OVRD_SB_EARC_CMDC_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) OVRD_SB_EARC_CMDC_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) hdptx_update_bits(hdptx, SB_REG010F, OVRD_SB_VREG_EN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) OVRD_SB_VREG_LPF_BYPASS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) OVRD_SB_VREG_EN(1) | OVRD_SB_VREG_LPF_BYPASS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) hdptx_update_bits(hdptx, SB_REG0123, OVRD_SB_READY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) OVRD_SB_READY(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) hdptx_update_bits(hdptx, SB_REG0103, SB_RX_RESCAL_DONE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) SB_RX_RESCAL_DONE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) hdptx_update_bits(hdptx, SB_REG0104, SB_EN_MASK, SB_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) hdptx_update_bits(hdptx, SB_REG0102, SB_RXTERM_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) SB_RXTERM_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) hdptx_update_bits(hdptx, SB_REG0105, SB_EARC_CMDC_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) SB_EARC_CMDC_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) hdptx_update_bits(hdptx, SB_REG010F, SB_VREG_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) SB_VREG_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) hdptx_update_bits(hdptx, SB_REG010F, OVRD_SB_VREG_LPF_BYPASS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) OVRD_SB_VREG_LPF_BYPASS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) udelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) hdptx_update_bits(hdptx, SB_REG010F, OVRD_SB_VREG_LPF_BYPASS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) OVRD_SB_VREG_LPF_BYPASS(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) hdptx_update_bits(hdptx, SB_REG0123, SB_READY_MASK, SB_READY(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static bool hdptx_phy_clk_pll_calc(unsigned int data_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct ropll_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) unsigned int fref = 24000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) unsigned int sdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) unsigned int fout = data_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) unsigned int fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) u32 mdiv, sdiv, n = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) unsigned long k = 0, lc, k_sub, lc_sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) for (sdiv = 16; sdiv >= 1; sdiv--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (sdiv % 2 && sdiv != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) fvco = fout * sdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (fvco < 2000000 || fvco > 4000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) mdiv = DIV_ROUND_UP(fvco, fref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (mdiv < 20 || mdiv > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (fref * mdiv - fvco) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) for (sdc = 264000; sdc <= 750000; sdc += fref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (sdc * n > fref * mdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (sdc > 750000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) rational_best_approximation(fref * mdiv - fvco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) sdc / 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) GENMASK(6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) GENMASK(7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) &k, &lc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) rational_best_approximation(sdc * n - fref * mdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) GENMASK(6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) GENMASK(7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) &k_sub, &lc_sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (sdiv < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) cfg->pms_mdiv = mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) cfg->pms_mdiv_afc = mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) cfg->pms_pdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) cfg->pms_refdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) cfg->pms_sdiv = sdiv - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) cfg->sdm_en = k > 0 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (cfg->sdm_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) cfg->sdm_deno = lc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) cfg->sdm_num_sign = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) cfg->sdm_num = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) cfg->sdc_n = n - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) cfg->sdc_num = k_sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) cfg->sdc_deno = lc_sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static int hdptx_ropll_cmn_config(struct rockchip_hdptx_phy *hdptx, unsigned long bit_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) int bus_width = phy_get_bus_width(hdptx->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct ropll_config *cfg = ropll_tmds_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct ropll_config rc = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_info(hdptx->dev, "%s bus_width:%x rate:%lu\n", __func__, bus_width, bit_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) hdptx->rate = bit_rate * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (color_depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) bit_rate = bit_rate * 10 / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) for (; cfg->bit_rate != ~0; cfg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (bit_rate == cfg->bit_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (cfg->bit_rate == ~0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (hdptx_phy_clk_pll_calc(bit_rate, &rc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) cfg = &rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) dev_err(hdptx->dev, "%s can't find pll cfg\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) cfg->pms_mdiv, cfg->pms_sdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) dev_dbg(hdptx->dev, "sdm_en=%u, k_sign=%u, k=%u, lc=%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev_dbg(hdptx->dev, "n=%u, k_sub=%u, lc_sub=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) cfg->sdc_n + 3, cfg->sdc_num, cfg->sdc_deno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) hdptx_pre_power_up(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) reset_control_assert(hdptx->ropll_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) reset_control_deassert(hdptx->ropll_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) hdptx_write(hdptx, CMN_REG0008, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) hdptx_write(hdptx, CMN_REG0009, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) hdptx_write(hdptx, CMN_REG000A, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) hdptx_write(hdptx, CMN_REG000B, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) hdptx_write(hdptx, CMN_REG000C, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) hdptx_write(hdptx, CMN_REG000D, 0xb8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) hdptx_write(hdptx, CMN_REG000E, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) hdptx_write(hdptx, CMN_REG000F, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) hdptx_write(hdptx, CMN_REG0010, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) hdptx_write(hdptx, CMN_REG0011, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) hdptx_write(hdptx, CMN_REG0012, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) hdptx_write(hdptx, CMN_REG0013, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) hdptx_write(hdptx, CMN_REG0014, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) hdptx_write(hdptx, CMN_REG0015, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) hdptx_write(hdptx, CMN_REG0016, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) hdptx_write(hdptx, CMN_REG0017, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) hdptx_write(hdptx, CMN_REG0018, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) hdptx_write(hdptx, CMN_REG0019, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) hdptx_write(hdptx, CMN_REG001A, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) hdptx_write(hdptx, CMN_REG001B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) hdptx_write(hdptx, CMN_REG001C, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) hdptx_write(hdptx, CMN_REG001D, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) hdptx_write(hdptx, CMN_REG001E, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) hdptx_write(hdptx, CMN_REG001F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) hdptx_write(hdptx, CMN_REG0020, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) hdptx_write(hdptx, CMN_REG0021, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) hdptx_write(hdptx, CMN_REG0022, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) hdptx_write(hdptx, CMN_REG0023, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) hdptx_write(hdptx, CMN_REG0024, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) hdptx_write(hdptx, CMN_REG0025, 0x53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) hdptx_write(hdptx, CMN_REG0026, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) hdptx_write(hdptx, CMN_REG0027, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) hdptx_write(hdptx, CMN_REG0028, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) hdptx_write(hdptx, CMN_REG0029, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) hdptx_write(hdptx, CMN_REG002A, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) hdptx_write(hdptx, CMN_REG002B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) hdptx_write(hdptx, CMN_REG002C, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) hdptx_write(hdptx, CMN_REG002D, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) hdptx_write(hdptx, CMN_REG002E, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) hdptx_write(hdptx, CMN_REG002F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) hdptx_write(hdptx, CMN_REG0030, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) hdptx_write(hdptx, CMN_REG0031, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) hdptx_write(hdptx, CMN_REG0032, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) hdptx_write(hdptx, CMN_REG0033, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) hdptx_write(hdptx, CMN_REG0034, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) hdptx_write(hdptx, CMN_REG0035, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) hdptx_write(hdptx, CMN_REG0038, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) hdptx_write(hdptx, CMN_REG0039, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) hdptx_write(hdptx, CMN_REG003A, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) hdptx_write(hdptx, CMN_REG003B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) hdptx_write(hdptx, CMN_REG003C, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) hdptx_write(hdptx, CMN_REG003D, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) hdptx_write(hdptx, CMN_REG003E, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) hdptx_write(hdptx, CMN_REG003F, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) hdptx_write(hdptx, CMN_REG0040, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) hdptx_write(hdptx, CMN_REG0041, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) hdptx_write(hdptx, CMN_REG0042, 0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) hdptx_write(hdptx, CMN_REG0043, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) hdptx_write(hdptx, CMN_REG0044, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) hdptx_write(hdptx, CMN_REG0045, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) hdptx_write(hdptx, CMN_REG0046, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) hdptx_write(hdptx, CMN_REG0047, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) hdptx_write(hdptx, CMN_REG0048, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) hdptx_write(hdptx, CMN_REG0049, 0xfa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) hdptx_write(hdptx, CMN_REG004A, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) hdptx_write(hdptx, CMN_REG004B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) hdptx_write(hdptx, CMN_REG004C, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) hdptx_write(hdptx, CMN_REG004D, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) hdptx_write(hdptx, CMN_REG004E, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) hdptx_write(hdptx, CMN_REG004F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) hdptx_write(hdptx, CMN_REG0050, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) hdptx_write(hdptx, CMN_REG0051, cfg->pms_mdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) hdptx_write(hdptx, CMN_REG0055, cfg->pms_mdiv_afc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) hdptx_write(hdptx, CMN_REG0059, (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) hdptx_write(hdptx, CMN_REG005A, (cfg->pms_sdiv << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) hdptx_write(hdptx, CMN_REG005C, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) hdptx_write(hdptx, CMN_REG005D, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) hdptx_write(hdptx, CMN_REG005E, 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) hdptx_update_bits(hdptx, CMN_REG005E, ROPLL_SDM_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ROPLL_SDM_EN(cfg->sdm_en));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (!cfg->sdm_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) hdptx_update_bits(hdptx, CMN_REG005E, 0xf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) hdptx_write(hdptx, CMN_REG005F, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) hdptx_update_bits(hdptx, CMN_REG0064, ROPLL_SDM_NUM_SIGN_RBR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ROPLL_SDM_NUM_SIGN_RBR(cfg->sdm_num_sign));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) hdptx_write(hdptx, CMN_REG0065, cfg->sdm_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) hdptx_write(hdptx, CMN_REG0060, cfg->sdm_deno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) hdptx_update_bits(hdptx, CMN_REG0069, ROPLL_SDC_N_RBR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ROPLL_SDC_N_RBR(cfg->sdc_n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) hdptx_write(hdptx, CMN_REG006C, cfg->sdc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) hdptx_write(hdptx, CMN_REG0070, cfg->sdc_deno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) hdptx_write(hdptx, CMN_REG006B, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) hdptx_write(hdptx, CMN_REG0073, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) hdptx_write(hdptx, CMN_REG0074, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) hdptx_write(hdptx, CMN_REG0075, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) hdptx_write(hdptx, CMN_REG0076, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) hdptx_write(hdptx, CMN_REG0077, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) hdptx_write(hdptx, CMN_REG0078, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) hdptx_write(hdptx, CMN_REG0079, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) hdptx_write(hdptx, CMN_REG007B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) hdptx_write(hdptx, CMN_REG007C, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) hdptx_write(hdptx, CMN_REG007D, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) hdptx_write(hdptx, CMN_REG007E, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) hdptx_write(hdptx, CMN_REG007F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) hdptx_write(hdptx, CMN_REG0080, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) hdptx_write(hdptx, CMN_REG0081, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) hdptx_write(hdptx, CMN_REG0082, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) hdptx_write(hdptx, CMN_REG0083, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) hdptx_write(hdptx, CMN_REG0084, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) hdptx_write(hdptx, CMN_REG0085, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_POSTDIV_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PLL_PCG_POSTDIV_SEL(cfg->pms_sdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_CLK_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) PLL_PCG_CLK_SEL(color_depth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_CLK_EN, PLL_PCG_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) hdptx_write(hdptx, CMN_REG0087, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) hdptx_write(hdptx, CMN_REG0089, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) hdptx_write(hdptx, CMN_REG008A, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) hdptx_write(hdptx, CMN_REG008B, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) hdptx_write(hdptx, CMN_REG008C, 0x2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) hdptx_write(hdptx, CMN_REG008D, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) hdptx_write(hdptx, CMN_REG008E, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) hdptx_write(hdptx, CMN_REG008F, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) hdptx_write(hdptx, CMN_REG0090, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) hdptx_write(hdptx, CMN_REG0091, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) hdptx_write(hdptx, CMN_REG0092, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) hdptx_write(hdptx, CMN_REG0093, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) hdptx_write(hdptx, CMN_REG0095, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) hdptx_write(hdptx, CMN_REG0097, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) hdptx_write(hdptx, CMN_REG0099, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) hdptx_write(hdptx, CMN_REG009A, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) hdptx_write(hdptx, CMN_REG009B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return hdptx_post_enable_pll(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static int hdptx_ropll_tmds_mode_config(struct rockchip_hdptx_phy *hdptx, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) u32 bit_rate = rate & DATA_RATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) hdptx_write(hdptx, SB_REG0114, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) hdptx_write(hdptx, SB_REG0115, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) hdptx_write(hdptx, SB_REG0116, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) hdptx_write(hdptx, SB_REG0117, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) hdptx_write(hdptx, LNTOP_REG0200, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (bit_rate >= 3400000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* For 1/40 bitrate clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) hdptx_write(hdptx, LNTOP_REG0201, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) hdptx_write(hdptx, LNTOP_REG0202, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) hdptx_write(hdptx, LNTOP_REG0203, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) hdptx_write(hdptx, LNTOP_REG0204, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) hdptx_write(hdptx, LNTOP_REG0205, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /* For 1/10 bitrate clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) hdptx_write(hdptx, LNTOP_REG0201, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) hdptx_write(hdptx, LNTOP_REG0202, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) hdptx_write(hdptx, LNTOP_REG0203, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) hdptx_write(hdptx, LNTOP_REG0204, 0x7c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) hdptx_write(hdptx, LNTOP_REG0205, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) hdptx_write(hdptx, LNTOP_REG0206, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) hdptx_write(hdptx, LANE_REG0303, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) hdptx_write(hdptx, LANE_REG0307, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) hdptx_write(hdptx, LANE_REG030A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) hdptx_write(hdptx, LANE_REG030B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) hdptx_write(hdptx, LANE_REG030C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) hdptx_write(hdptx, LANE_REG030D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) hdptx_write(hdptx, LANE_REG030E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) hdptx_write(hdptx, LANE_REG0310, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) hdptx_write(hdptx, LANE_REG0311, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) hdptx_write(hdptx, LANE_REG0312, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) hdptx_write(hdptx, LANE_REG0316, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) hdptx_write(hdptx, LANE_REG031B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) hdptx_write(hdptx, LANE_REG031E, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) hdptx_write(hdptx, LANE_REG031F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) hdptx_write(hdptx, LANE_REG0320, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) hdptx_write(hdptx, LANE_REG0403, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) hdptx_write(hdptx, LANE_REG0407, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) hdptx_write(hdptx, LANE_REG040A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) hdptx_write(hdptx, LANE_REG040B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) hdptx_write(hdptx, LANE_REG040C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) hdptx_write(hdptx, LANE_REG040D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) hdptx_write(hdptx, LANE_REG040E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) hdptx_write(hdptx, LANE_REG0410, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) hdptx_write(hdptx, LANE_REG0411, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) hdptx_write(hdptx, LANE_REG0412, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) hdptx_write(hdptx, LANE_REG0416, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) hdptx_write(hdptx, LANE_REG041B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) hdptx_write(hdptx, LANE_REG041E, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) hdptx_write(hdptx, LANE_REG041F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) hdptx_write(hdptx, LANE_REG0420, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) hdptx_write(hdptx, LANE_REG0503, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) hdptx_write(hdptx, LANE_REG0507, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) hdptx_write(hdptx, LANE_REG050A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) hdptx_write(hdptx, LANE_REG050B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) hdptx_write(hdptx, LANE_REG050C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) hdptx_write(hdptx, LANE_REG050D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) hdptx_write(hdptx, LANE_REG050E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) hdptx_write(hdptx, LANE_REG0510, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) hdptx_write(hdptx, LANE_REG0511, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) hdptx_write(hdptx, LANE_REG0512, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) hdptx_write(hdptx, LANE_REG0516, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) hdptx_write(hdptx, LANE_REG051B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) hdptx_write(hdptx, LANE_REG051E, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) hdptx_write(hdptx, LANE_REG051F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) hdptx_write(hdptx, LANE_REG0520, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) hdptx_write(hdptx, LANE_REG0603, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) hdptx_write(hdptx, LANE_REG0607, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) hdptx_write(hdptx, LANE_REG060A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) hdptx_write(hdptx, LANE_REG060B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) hdptx_write(hdptx, LANE_REG060C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) hdptx_write(hdptx, LANE_REG060D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) hdptx_write(hdptx, LANE_REG060E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) hdptx_write(hdptx, LANE_REG0610, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) hdptx_write(hdptx, LANE_REG0611, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) hdptx_write(hdptx, LANE_REG0612, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) hdptx_write(hdptx, LANE_REG0616, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) hdptx_write(hdptx, LANE_REG061B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) hdptx_write(hdptx, LANE_REG061E, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) hdptx_write(hdptx, LANE_REG061F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) hdptx_write(hdptx, LANE_REG0620, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) hdptx_write(hdptx, LANE_REG0303, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) hdptx_write(hdptx, LANE_REG0403, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) hdptx_write(hdptx, LANE_REG0503, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) hdptx_write(hdptx, LANE_REG0603, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) hdptx_write(hdptx, LANE_REG0305, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) hdptx_write(hdptx, LANE_REG0405, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) hdptx_write(hdptx, LANE_REG0505, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) hdptx_write(hdptx, LANE_REG0605, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) hdptx_write(hdptx, LANE_REG0306, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) hdptx_write(hdptx, LANE_REG0406, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) hdptx_write(hdptx, LANE_REG0506, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) hdptx_write(hdptx, LANE_REG0606, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (hdptx->earc_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) hdptx_earc_config(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return hdptx_post_enable_lane(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static int hdptx_ropll_frl_mode_config(struct rockchip_hdptx_phy *hdptx, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) u32 bit_rate = rate & DATA_RATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) u8 color_depth = (rate & COLOR_DEPTH_MASK) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct ropll_config *cfg = ropll_frl_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) for (; cfg->bit_rate != ~0; cfg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (bit_rate == cfg->bit_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (cfg->bit_rate == ~0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) dev_err(hdptx->dev, "%s can't find pll cfg\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) hdptx_pre_power_up(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) reset_control_assert(hdptx->ropll_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) reset_control_deassert(hdptx->ropll_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) hdptx_write(hdptx, CMN_REG0008, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) hdptx_write(hdptx, CMN_REG0009, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) hdptx_write(hdptx, CMN_REG000A, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) hdptx_write(hdptx, CMN_REG000B, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) hdptx_write(hdptx, CMN_REG000C, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) hdptx_write(hdptx, CMN_REG000D, 0xb8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) hdptx_write(hdptx, CMN_REG000E, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) hdptx_write(hdptx, CMN_REG000F, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) hdptx_write(hdptx, CMN_REG0010, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) hdptx_write(hdptx, CMN_REG0011, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) hdptx_write(hdptx, CMN_REG0012, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) hdptx_write(hdptx, CMN_REG0013, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) hdptx_write(hdptx, CMN_REG0014, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) hdptx_write(hdptx, CMN_REG0015, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) hdptx_write(hdptx, CMN_REG0016, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) hdptx_write(hdptx, CMN_REG0017, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) hdptx_write(hdptx, CMN_REG0018, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) hdptx_write(hdptx, CMN_REG0019, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) hdptx_write(hdptx, CMN_REG001A, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) hdptx_write(hdptx, CMN_REG001B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) hdptx_write(hdptx, CMN_REG001C, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) hdptx_write(hdptx, CMN_REG001D, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) hdptx_write(hdptx, CMN_REG001E, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) hdptx_write(hdptx, CMN_REG001F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) hdptx_write(hdptx, CMN_REG0020, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) hdptx_write(hdptx, CMN_REG0021, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) hdptx_write(hdptx, CMN_REG0022, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) hdptx_write(hdptx, CMN_REG0023, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) hdptx_write(hdptx, CMN_REG0025, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) hdptx_write(hdptx, CMN_REG0026, 0x53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) hdptx_write(hdptx, CMN_REG0027, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) hdptx_write(hdptx, CMN_REG0028, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) hdptx_write(hdptx, CMN_REG0029, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) hdptx_write(hdptx, CMN_REG002A, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) hdptx_write(hdptx, CMN_REG002B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) hdptx_write(hdptx, CMN_REG002C, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) hdptx_write(hdptx, CMN_REG002D, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) hdptx_write(hdptx, CMN_REG002E, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) hdptx_write(hdptx, CMN_REG002F, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) hdptx_write(hdptx, CMN_REG0030, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) hdptx_write(hdptx, CMN_REG0031, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) hdptx_write(hdptx, CMN_REG0032, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) hdptx_write(hdptx, CMN_REG0033, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) hdptx_write(hdptx, CMN_REG0034, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) hdptx_write(hdptx, CMN_REG0035, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) hdptx_write(hdptx, CMN_REG0038, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) hdptx_write(hdptx, CMN_REG0039, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) hdptx_write(hdptx, CMN_REG003A, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) hdptx_write(hdptx, CMN_REG003B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) hdptx_write(hdptx, CMN_REG003C, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) hdptx_write(hdptx, CMN_REG003D, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) hdptx_write(hdptx, CMN_REG003E, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) hdptx_write(hdptx, CMN_REG003F, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) hdptx_write(hdptx, CMN_REG0040, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) hdptx_write(hdptx, CMN_REG0041, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) hdptx_write(hdptx, CMN_REG0042, 0xb8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) hdptx_write(hdptx, CMN_REG0043, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) hdptx_write(hdptx, CMN_REG0044, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) hdptx_write(hdptx, CMN_REG0045, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) hdptx_write(hdptx, CMN_REG0046, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) hdptx_write(hdptx, CMN_REG0047, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) hdptx_write(hdptx, CMN_REG0048, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) hdptx_write(hdptx, CMN_REG0049, 0xfa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) hdptx_write(hdptx, CMN_REG004A, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) hdptx_write(hdptx, CMN_REG004B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) hdptx_write(hdptx, CMN_REG004C, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) hdptx_write(hdptx, CMN_REG004D, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) hdptx_write(hdptx, CMN_REG004E, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) hdptx_write(hdptx, CMN_REG004F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) hdptx_write(hdptx, CMN_REG0050, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) hdptx_write(hdptx, CMN_REG0051, cfg->pms_mdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) hdptx_write(hdptx, CMN_REG0055, cfg->pms_mdiv_afc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) hdptx_write(hdptx, CMN_REG0059, (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) hdptx_write(hdptx, CMN_REG005A, (cfg->pms_sdiv << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) hdptx_write(hdptx, CMN_REG005C, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) hdptx_write(hdptx, CMN_REG005D, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) hdptx_update_bits(hdptx, CMN_REG005E, ROPLL_SDM_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) ROPLL_SDM_EN(cfg->sdm_en));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (!cfg->sdm_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) hdptx_update_bits(hdptx, CMN_REG005E, 0xf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) hdptx_write(hdptx, CMN_REG005F, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) hdptx_update_bits(hdptx, CMN_REG0064, ROPLL_SDM_NUM_SIGN_RBR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ROPLL_SDM_NUM_SIGN_RBR(cfg->sdm_num_sign));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) hdptx_write(hdptx, CMN_REG0065, cfg->sdm_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) hdptx_write(hdptx, CMN_REG0060, cfg->sdm_deno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) hdptx_update_bits(hdptx, CMN_REG0069, ROPLL_SDC_N_RBR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ROPLL_SDC_N_RBR(cfg->sdc_n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) hdptx_write(hdptx, CMN_REG006C, cfg->sdc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) hdptx_write(hdptx, CMN_REG0070, cfg->sdc_deno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) hdptx_write(hdptx, CMN_REG006B, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) hdptx_write(hdptx, CMN_REG0073, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) hdptx_write(hdptx, CMN_REG0074, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) hdptx_write(hdptx, CMN_REG0075, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) hdptx_write(hdptx, CMN_REG0076, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) hdptx_write(hdptx, CMN_REG0077, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) hdptx_write(hdptx, CMN_REG0078, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) hdptx_write(hdptx, CMN_REG0079, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) hdptx_write(hdptx, CMN_REG007B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) hdptx_write(hdptx, CMN_REG007C, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) hdptx_write(hdptx, CMN_REG007D, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) hdptx_write(hdptx, CMN_REG007E, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) hdptx_write(hdptx, CMN_REG007F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) hdptx_write(hdptx, CMN_REG0080, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) hdptx_write(hdptx, CMN_REG0081, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) hdptx_write(hdptx, CMN_REG0082, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) hdptx_write(hdptx, CMN_REG0083, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) hdptx_write(hdptx, CMN_REG0084, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) hdptx_write(hdptx, CMN_REG0085, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) hdptx_write(hdptx, CMN_REG0086, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_POSTDIV_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) PLL_PCG_POSTDIV_SEL(cfg->pms_sdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_CLK_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) PLL_PCG_CLK_SEL(color_depth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) hdptx_write(hdptx, CMN_REG0087, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) hdptx_write(hdptx, CMN_REG0089, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) hdptx_write(hdptx, CMN_REG008A, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) hdptx_write(hdptx, CMN_REG008B, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) hdptx_write(hdptx, CMN_REG008C, 0x2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) hdptx_write(hdptx, CMN_REG008D, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) hdptx_write(hdptx, CMN_REG008E, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) hdptx_write(hdptx, CMN_REG008F, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) hdptx_write(hdptx, CMN_REG0090, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) hdptx_write(hdptx, CMN_REG0091, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) hdptx_write(hdptx, CMN_REG0092, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) hdptx_write(hdptx, CMN_REG0093, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) hdptx_write(hdptx, CMN_REG0094, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) hdptx_write(hdptx, CMN_REG0097, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) hdptx_write(hdptx, CMN_REG0099, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) hdptx_write(hdptx, CMN_REG009A, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) hdptx_write(hdptx, CMN_REG009B, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) hdptx_write(hdptx, SB_REG0114, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) hdptx_write(hdptx, SB_REG0115, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) hdptx_write(hdptx, SB_REG0116, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) hdptx_write(hdptx, SB_REG0117, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) hdptx_write(hdptx, LNTOP_REG0200, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) hdptx_write(hdptx, LNTOP_REG0201, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) hdptx_write(hdptx, LNTOP_REG0202, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) hdptx_write(hdptx, LNTOP_REG0203, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) hdptx_write(hdptx, LNTOP_REG0204, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) hdptx_write(hdptx, LNTOP_REG0205, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) hdptx_write(hdptx, LNTOP_REG0206, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) hdptx_write(hdptx, LNTOP_REG0207, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) hdptx_write(hdptx, LANE_REG0303, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) hdptx_write(hdptx, LANE_REG0307, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) hdptx_write(hdptx, LANE_REG030A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) hdptx_write(hdptx, LANE_REG030B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) hdptx_write(hdptx, LANE_REG030C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) hdptx_write(hdptx, LANE_REG030D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) hdptx_write(hdptx, LANE_REG030E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) hdptx_write(hdptx, LANE_REG0310, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) hdptx_write(hdptx, LANE_REG0311, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) hdptx_write(hdptx, LANE_REG0312, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) hdptx_write(hdptx, LANE_REG0316, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) hdptx_write(hdptx, LANE_REG031B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) hdptx_write(hdptx, LANE_REG031F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) hdptx_write(hdptx, LANE_REG0320, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) hdptx_write(hdptx, LANE_REG0403, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) hdptx_write(hdptx, LANE_REG0407, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) hdptx_write(hdptx, LANE_REG040A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) hdptx_write(hdptx, LANE_REG040B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) hdptx_write(hdptx, LANE_REG040C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) hdptx_write(hdptx, LANE_REG040D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) hdptx_write(hdptx, LANE_REG040E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) hdptx_write(hdptx, LANE_REG0410, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) hdptx_write(hdptx, LANE_REG0411, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) hdptx_write(hdptx, LANE_REG0412, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) hdptx_write(hdptx, LANE_REG0416, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) hdptx_write(hdptx, LANE_REG041B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) hdptx_write(hdptx, LANE_REG041F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) hdptx_write(hdptx, LANE_REG0420, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) hdptx_write(hdptx, LANE_REG0503, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) hdptx_write(hdptx, LANE_REG0507, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) hdptx_write(hdptx, LANE_REG050A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) hdptx_write(hdptx, LANE_REG050B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) hdptx_write(hdptx, LANE_REG050C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) hdptx_write(hdptx, LANE_REG050D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) hdptx_write(hdptx, LANE_REG050E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) hdptx_write(hdptx, LANE_REG0510, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) hdptx_write(hdptx, LANE_REG0511, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) hdptx_write(hdptx, LANE_REG0512, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) hdptx_write(hdptx, LANE_REG0516, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) hdptx_write(hdptx, LANE_REG051B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) hdptx_write(hdptx, LANE_REG051F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) hdptx_write(hdptx, LANE_REG0520, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) hdptx_write(hdptx, LANE_REG0603, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) hdptx_write(hdptx, LANE_REG0607, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) hdptx_write(hdptx, LANE_REG060A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) hdptx_write(hdptx, LANE_REG060B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) hdptx_write(hdptx, LANE_REG060C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) hdptx_write(hdptx, LANE_REG060D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) hdptx_write(hdptx, LANE_REG060E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) hdptx_write(hdptx, LANE_REG0610, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) hdptx_write(hdptx, LANE_REG0611, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) hdptx_write(hdptx, LANE_REG0612, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) hdptx_write(hdptx, LANE_REG0616, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) hdptx_write(hdptx, LANE_REG061B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) hdptx_write(hdptx, LANE_REG061F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) hdptx_write(hdptx, LANE_REG0620, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (hdptx->earc_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) hdptx_earc_config(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) return hdptx_post_power_up(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static int hdptx_lcpll_cmn_config(struct rockchip_hdptx_phy *hdptx, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) u32 bit_rate = rate & DATA_RATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) u8 color_depth = (rate & COLOR_DEPTH_MASK) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) struct lcpll_config *cfg = lcpll_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) dev_info(hdptx->dev, "%s rate:%lu\n", __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) hdptx->rate = bit_rate * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) for (; cfg->bit_rate != ~0; cfg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (bit_rate == cfg->bit_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (cfg->bit_rate == ~0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) dev_err(hdptx->dev, "can't find frl rate, phy pll init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) hdptx_pre_power_up(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) hdptx_update_bits(hdptx, CMN_REG0008, LCPLL_EN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) LCPLL_LCVCO_MODE_EN_MASK, LCPLL_EN(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) LCPLL_LCVCO_MODE_EN(cfg->lcvco_mode_en));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) hdptx_write(hdptx, CMN_REG0009, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) hdptx_write(hdptx, CMN_REG000A, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) hdptx_write(hdptx, CMN_REG000B, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) hdptx_write(hdptx, CMN_REG000C, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) hdptx_write(hdptx, CMN_REG000D, 0xb8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) hdptx_write(hdptx, CMN_REG000E, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) hdptx_write(hdptx, CMN_REG000F, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) hdptx_write(hdptx, CMN_REG0010, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) hdptx_write(hdptx, CMN_REG0011, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) hdptx_write(hdptx, CMN_REG0012, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) hdptx_write(hdptx, CMN_REG0013, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) hdptx_write(hdptx, CMN_REG0014, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) hdptx_write(hdptx, CMN_REG0015, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) hdptx_write(hdptx, CMN_REG0016, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) hdptx_write(hdptx, CMN_REG0017, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) hdptx_write(hdptx, CMN_REG0018, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) hdptx_write(hdptx, CMN_REG0019, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) hdptx_write(hdptx, CMN_REG001A, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) hdptx_write(hdptx, CMN_REG001B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) hdptx_write(hdptx, CMN_REG001C, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) hdptx_write(hdptx, CMN_REG001D, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) hdptx_update_bits(hdptx, CMN_REG001E, LCPLL_PI_EN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) LCPLL_100M_CLK_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) LCPLL_PI_EN(cfg->pi_en) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) LCPLL_100M_CLK_EN(cfg->clk_en_100m));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) hdptx_write(hdptx, CMN_REG001F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) hdptx_write(hdptx, CMN_REG0020, cfg->pms_mdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) hdptx_write(hdptx, CMN_REG0021, cfg->pms_mdiv_afc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) hdptx_write(hdptx, CMN_REG0022, (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) hdptx_write(hdptx, CMN_REG0023, (cfg->pms_sdiv << 4) | cfg->pms_sdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) hdptx_write(hdptx, CMN_REG0025, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) hdptx_write(hdptx, CMN_REG0026, 0x53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) hdptx_write(hdptx, CMN_REG0027, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) hdptx_write(hdptx, CMN_REG0028, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) hdptx_write(hdptx, CMN_REG0029, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) hdptx_write(hdptx, CMN_REG002A, cfg->sdm_deno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) hdptx_write(hdptx, CMN_REG002B, cfg->sdm_num_sign);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) hdptx_write(hdptx, CMN_REG002C, cfg->sdm_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) hdptx_update_bits(hdptx, CMN_REG002D, LCPLL_SDC_N_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) LCPLL_SDC_N(cfg->sdc_n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) hdptx_write(hdptx, CMN_REG002E, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) hdptx_write(hdptx, CMN_REG002F, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) hdptx_write(hdptx, CMN_REG0030, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) hdptx_write(hdptx, CMN_REG0031, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) hdptx_write(hdptx, CMN_REG0032, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) hdptx_write(hdptx, CMN_REG0033, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) hdptx_write(hdptx, CMN_REG0034, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) hdptx_write(hdptx, CMN_REG0035, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) hdptx_write(hdptx, CMN_REG0038, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) hdptx_write(hdptx, CMN_REG0039, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) hdptx_write(hdptx, CMN_REG003A, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) hdptx_write(hdptx, CMN_REG003B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) hdptx_write(hdptx, CMN_REG003C, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) hdptx_write(hdptx, CMN_REG003D, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) hdptx_write(hdptx, CMN_REG003E, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) hdptx_write(hdptx, CMN_REG003F, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) hdptx_write(hdptx, CMN_REG0040, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) hdptx_write(hdptx, CMN_REG0041, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) hdptx_write(hdptx, CMN_REG0042, 0xb8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) hdptx_write(hdptx, CMN_REG0043, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) hdptx_write(hdptx, CMN_REG0044, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) hdptx_write(hdptx, CMN_REG0045, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) hdptx_write(hdptx, CMN_REG0046, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) hdptx_write(hdptx, CMN_REG0047, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) hdptx_write(hdptx, CMN_REG0048, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) hdptx_write(hdptx, CMN_REG0049, 0xfa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) hdptx_write(hdptx, CMN_REG004A, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) hdptx_write(hdptx, CMN_REG004B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) hdptx_write(hdptx, CMN_REG004C, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) hdptx_write(hdptx, CMN_REG004D, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) hdptx_write(hdptx, CMN_REG004E, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) hdptx_write(hdptx, CMN_REG004F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) hdptx_write(hdptx, CMN_REG0050, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) hdptx_write(hdptx, CMN_REG0051, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) hdptx_write(hdptx, CMN_REG0055, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) hdptx_write(hdptx, CMN_REG0059, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) hdptx_write(hdptx, CMN_REG005A, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) hdptx_write(hdptx, CMN_REG005C, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) hdptx_write(hdptx, CMN_REG005D, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) hdptx_write(hdptx, CMN_REG005E, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) hdptx_write(hdptx, CMN_REG005F, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) hdptx_write(hdptx, CMN_REG0060, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) hdptx_write(hdptx, CMN_REG0064, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) hdptx_write(hdptx, CMN_REG0065, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) hdptx_write(hdptx, CMN_REG0069, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) hdptx_write(hdptx, CMN_REG006B, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) hdptx_write(hdptx, CMN_REG006C, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) hdptx_write(hdptx, CMN_REG0070, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) hdptx_write(hdptx, CMN_REG0073, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) hdptx_write(hdptx, CMN_REG0074, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) hdptx_write(hdptx, CMN_REG0075, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) hdptx_write(hdptx, CMN_REG0076, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) hdptx_write(hdptx, CMN_REG0077, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) hdptx_write(hdptx, CMN_REG0078, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) hdptx_write(hdptx, CMN_REG0079, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) hdptx_write(hdptx, CMN_REG007B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) hdptx_write(hdptx, CMN_REG007C, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) hdptx_write(hdptx, CMN_REG007D, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) hdptx_write(hdptx, CMN_REG007E, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) hdptx_write(hdptx, CMN_REG007F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) hdptx_write(hdptx, CMN_REG0080, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) hdptx_write(hdptx, CMN_REG0081, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) hdptx_write(hdptx, CMN_REG0082, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) hdptx_write(hdptx, CMN_REG0083, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) hdptx_write(hdptx, CMN_REG0084, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) hdptx_write(hdptx, CMN_REG0085, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) hdptx_write(hdptx, CMN_REG0086, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_POSTDIV_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) PLL_PCG_POSTDIV_SEL(cfg->pms_sdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_CLK_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) PLL_PCG_CLK_SEL(color_depth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) hdptx_write(hdptx, CMN_REG0087, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) hdptx_write(hdptx, CMN_REG0089, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) hdptx_write(hdptx, CMN_REG008A, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) hdptx_write(hdptx, CMN_REG008B, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) hdptx_write(hdptx, CMN_REG008C, 0x2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) hdptx_write(hdptx, CMN_REG008D, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) hdptx_write(hdptx, CMN_REG008E, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) hdptx_write(hdptx, CMN_REG008F, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) hdptx_write(hdptx, CMN_REG0090, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) hdptx_write(hdptx, CMN_REG0091, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) hdptx_write(hdptx, CMN_REG0092, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) hdptx_write(hdptx, CMN_REG0093, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) hdptx_write(hdptx, CMN_REG0095, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) hdptx_write(hdptx, CMN_REG0097, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) hdptx_write(hdptx, CMN_REG0099, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) hdptx_write(hdptx, CMN_REG009A, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) hdptx_write(hdptx, CMN_REG009B, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) return hdptx_post_enable_pll(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static int hdptx_lcpll_frl_mode_config(struct rockchip_hdptx_phy *hdptx, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) hdptx_write(hdptx, SB_REG0114, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) hdptx_write(hdptx, SB_REG0115, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) hdptx_write(hdptx, SB_REG0116, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) hdptx_write(hdptx, SB_REG0117, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) hdptx_write(hdptx, LNTOP_REG0200, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) hdptx_write(hdptx, LNTOP_REG0201, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) hdptx_write(hdptx, LNTOP_REG0202, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) hdptx_write(hdptx, LNTOP_REG0203, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) hdptx_write(hdptx, LNTOP_REG0204, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) hdptx_write(hdptx, LNTOP_REG0205, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) hdptx_write(hdptx, LNTOP_REG0206, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) hdptx_write(hdptx, LANE_REG0303, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) hdptx_write(hdptx, LANE_REG0307, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) hdptx_write(hdptx, LANE_REG030A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) hdptx_write(hdptx, LANE_REG030B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) hdptx_write(hdptx, LANE_REG030C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) hdptx_write(hdptx, LANE_REG030D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) hdptx_write(hdptx, LANE_REG030E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) hdptx_write(hdptx, LANE_REG0310, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) hdptx_write(hdptx, LANE_REG0311, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) hdptx_write(hdptx, LANE_REG0312, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) hdptx_write(hdptx, LANE_REG0316, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) hdptx_write(hdptx, LANE_REG031B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) hdptx_write(hdptx, LANE_REG031F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) hdptx_write(hdptx, LANE_REG0320, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) hdptx_write(hdptx, LANE_REG0403, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) hdptx_write(hdptx, LANE_REG0407, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) hdptx_write(hdptx, LANE_REG040A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) hdptx_write(hdptx, LANE_REG040B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) hdptx_write(hdptx, LANE_REG040C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) hdptx_write(hdptx, LANE_REG040D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) hdptx_write(hdptx, LANE_REG040E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) hdptx_write(hdptx, LANE_REG0410, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) hdptx_write(hdptx, LANE_REG0411, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) hdptx_write(hdptx, LANE_REG0412, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) hdptx_write(hdptx, LANE_REG0416, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) hdptx_write(hdptx, LANE_REG041B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) hdptx_write(hdptx, LANE_REG041F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) hdptx_write(hdptx, LANE_REG0420, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) hdptx_write(hdptx, LANE_REG0503, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) hdptx_write(hdptx, LANE_REG0507, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) hdptx_write(hdptx, LANE_REG050A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) hdptx_write(hdptx, LANE_REG050B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) hdptx_write(hdptx, LANE_REG050C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) hdptx_write(hdptx, LANE_REG050D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) hdptx_write(hdptx, LANE_REG050E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) hdptx_write(hdptx, LANE_REG0510, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) hdptx_write(hdptx, LANE_REG0511, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) hdptx_write(hdptx, LANE_REG0512, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) hdptx_write(hdptx, LANE_REG0516, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) hdptx_write(hdptx, LANE_REG051B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) hdptx_write(hdptx, LANE_REG051F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) hdptx_write(hdptx, LANE_REG0520, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) hdptx_write(hdptx, LANE_REG0603, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) hdptx_write(hdptx, LANE_REG0607, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) hdptx_write(hdptx, LANE_REG060A, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) hdptx_write(hdptx, LANE_REG060B, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) hdptx_write(hdptx, LANE_REG060C, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) hdptx_write(hdptx, LANE_REG060D, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) hdptx_write(hdptx, LANE_REG060E, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) hdptx_write(hdptx, LANE_REG0610, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) hdptx_write(hdptx, LANE_REG0611, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) hdptx_write(hdptx, LANE_REG0612, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) hdptx_write(hdptx, LANE_REG0616, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) hdptx_write(hdptx, LANE_REG061B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) hdptx_write(hdptx, LANE_REG061F, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) hdptx_write(hdptx, LANE_REG0620, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) hdptx_write(hdptx, LANE_REG0303, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) hdptx_write(hdptx, LANE_REG0403, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) hdptx_write(hdptx, LANE_REG0503, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) hdptx_write(hdptx, LANE_REG0603, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) hdptx_write(hdptx, LANE_REG0305, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) hdptx_write(hdptx, LANE_REG0405, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) hdptx_write(hdptx, LANE_REG0505, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) hdptx_write(hdptx, LANE_REG0605, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) hdptx_write(hdptx, LANE_REG0306, 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) hdptx_write(hdptx, LANE_REG0406, 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) hdptx_write(hdptx, LANE_REG0506, 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) hdptx_write(hdptx, LANE_REG0606, 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) hdptx_write(hdptx, LANE_REG0305, 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) hdptx_write(hdptx, LANE_REG0405, 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) hdptx_write(hdptx, LANE_REG0505, 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) hdptx_write(hdptx, LANE_REG0605, 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) hdptx_write(hdptx, LANE_REG0304, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) hdptx_write(hdptx, LANE_REG0404, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) hdptx_write(hdptx, LANE_REG0504, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) hdptx_write(hdptx, LANE_REG0604, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (hdptx->earc_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) hdptx_earc_config(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return hdptx_post_enable_lane(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) static int rockchip_hdptx_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) int bus_width = phy_get_bus_width(hdptx->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) int bit_rate = bus_width & DATA_RATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) dev_info(hdptx->dev, "bus_width:0x%x,bit_rate:%d\n", bus_width, bit_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) if (bus_width & HDMI_EARC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) hdptx->earc_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) hdptx->earc_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (bus_width & HDMI_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) if (bit_rate > 24000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return hdptx_lcpll_frl_mode_config(hdptx, bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) return hdptx_ropll_frl_mode_config(hdptx, bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) return hdptx_ropll_tmds_mode_config(hdptx, bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) static int rockchip_hdptx_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) /* disable phy lane output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) hdptx_write(hdptx, LNTOP_REG0207, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static const struct phy_ops rockchip_hdptx_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .power_on = rockchip_hdptx_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .power_off = rockchip_hdptx_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static const struct of_device_id rockchip_hdptx_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) { .compatible = "rockchip,rk3588-hdptx-phy-hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) MODULE_DEVICE_TABLE(of, rockchip_hdptx_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) static void rockchip_hdptx_phy_runtime_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) struct rockchip_hdptx_phy *hdptx = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) clk_bulk_unprepare(hdptx->nr_clks, hdptx->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) pm_runtime_disable(hdptx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) static unsigned long hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) struct rockchip_hdptx_phy *hdptx = to_rockchip_hdptx_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) return hdptx->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static long hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) struct ropll_config *cfg = ropll_tmds_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) u32 bit_rate = rate / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (rate > HDMI20_MAX_RATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) for (; cfg->bit_rate != ~0; cfg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (bit_rate == cfg->bit_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) if (cfg->bit_rate == ~0 && !hdptx_phy_clk_pll_calc(bit_rate, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static int hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) struct rockchip_hdptx_phy *hdptx = to_rockchip_hdptx_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) if (hdptx_grf_read(hdptx, GRF_HDPTX_STATUS) & HDPTX_O_PLL_LOCK_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) hdptx_phy_disable(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) if (rate > HDMI20_MAX_RATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) return hdptx_lcpll_cmn_config(hdptx, rate / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) return hdptx_ropll_cmn_config(hdptx, rate / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static int hdptx_phy_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) struct rockchip_hdptx_phy *hdptx = to_rockchip_hdptx_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (hdptx->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) hdptx->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) ret = clk_bulk_enable(hdptx->nr_clks, hdptx->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) dev_err(hdptx->dev, "failed to enable clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (hdptx->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (hdptx->rate > HDMI20_MAX_RATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ret = hdptx_lcpll_cmn_config(hdptx, hdptx->rate / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) ret = hdptx_ropll_cmn_config(hdptx, hdptx->rate / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) dev_err(hdptx->dev, "hdmi phy pll init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) hdptx->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) static void hdptx_phy_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) struct rockchip_hdptx_phy *hdptx = to_rockchip_hdptx_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) if (hdptx->count > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) hdptx->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) if (hdptx_grf_read(hdptx, GRF_HDPTX_STATUS) & HDPTX_O_PLL_LOCK_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) hdptx_phy_disable(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) clk_bulk_disable(hdptx->nr_clks, hdptx->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) hdptx->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) static const struct clk_ops hdptx_phy_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .recalc_rate = hdptx_phy_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .round_rate = hdptx_phy_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .set_rate = hdptx_phy_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .enable = hdptx_phy_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .disable = hdptx_phy_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) static int rockchip_hdptx_phy_clk_register(struct rockchip_hdptx_phy *hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) struct device *dev = hdptx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) struct device_node *clk_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) struct clk *refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) clk_np = of_get_child_by_name(np, "clk-port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) if (!clk_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) pdev = of_platform_device_create(clk_np, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) refclk = devm_clk_get(dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (IS_ERR(refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) dev_err(dev, "failed to get ref clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) return PTR_ERR(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) parent_name = __clk_get_name(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) init.flags = CLK_GET_RATE_NOCACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (!hdptx->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) init.name = "clk_hdmiphy_pixel0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) init.name = "clk_hdmiphy_pixel1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) init.ops = &hdptx_phy_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) /* optional override of the clock name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) of_property_read_string(np, "clock-output-names", &init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) hdptx->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) hdptx->dclk = devm_clk_register(&pdev->dev, &hdptx->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) if (IS_ERR(hdptx->dclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) ret = PTR_ERR(hdptx->dclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) dev_err(dev, "failed to register clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) ret = of_clk_add_provider(clk_np, of_clk_src_simple_get, hdptx->dclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) dev_err(dev, "failed to register OF clock provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) static int rockchip_hdptx_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) struct rockchip_hdptx_phy *hdptx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) if (!hdptx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) hdptx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) hdptx->id = of_alias_get_id(dev->of_node, "hdptxhdmi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) if (hdptx->id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) hdptx->id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) ret = devm_clk_bulk_get_all(dev, &hdptx->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (ret < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) return dev_err_probe(dev, ret, "failed to get clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) hdptx->nr_clks = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) ret = clk_bulk_prepare(hdptx->nr_clks, hdptx->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) dev_err(hdptx->dev, "failed to prepare clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) hdptx->regmap = devm_regmap_init_mmio(dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) &rockchip_hdptx_phy_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if (IS_ERR(hdptx->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) ret = PTR_ERR(hdptx->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) dev_err(dev, "failed to init regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) hdptx->phy_reset = devm_reset_control_get(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) if (IS_ERR(hdptx->phy_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) ret = PTR_ERR(hdptx->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) dev_err(dev, "failed to get phy reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) hdptx->apb_reset = devm_reset_control_get(dev, "apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) if (IS_ERR(hdptx->apb_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) ret = PTR_ERR(hdptx->apb_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) dev_err(dev, "failed to get apb reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) hdptx->init_reset = devm_reset_control_get(dev, "init");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) if (IS_ERR(hdptx->init_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) ret = PTR_ERR(hdptx->init_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) dev_err(dev, "failed to get init reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) hdptx->cmn_reset = devm_reset_control_get(dev, "cmn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) if (IS_ERR(hdptx->cmn_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) ret = PTR_ERR(hdptx->cmn_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) dev_err(dev, "failed to get apb reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) hdptx->lane_reset = devm_reset_control_get(dev, "lane");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) if (IS_ERR(hdptx->lane_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) ret = PTR_ERR(hdptx->lane_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) dev_err(dev, "failed to get lane reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) hdptx->ropll_reset = devm_reset_control_get(dev, "ropll");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) if (IS_ERR(hdptx->ropll_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) ret = PTR_ERR(hdptx->ropll_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) dev_err(dev, "failed to get ropll reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) hdptx->lcpll_reset = devm_reset_control_get(dev, "lcpll");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (IS_ERR(hdptx->lcpll_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) ret = PTR_ERR(hdptx->lcpll_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) dev_err(dev, "failed to get lcpll reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) hdptx->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) if (IS_ERR(hdptx->grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) ret = PTR_ERR(hdptx->grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) dev_err(hdptx->dev, "Unable to get rockchip,grf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) hdptx->phy = devm_phy_create(dev, NULL, &rockchip_hdptx_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (IS_ERR(hdptx->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) dev_err(dev, "failed to create HDMI PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) ret = PTR_ERR(hdptx->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) phy_set_drvdata(hdptx->phy, hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) phy_set_bus_width(hdptx->phy, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) ret = devm_add_action_or_reset(dev, rockchip_hdptx_phy_runtime_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) dev_err(dev, "failed to register PHY provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) ret = PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) reset_control_deassert(hdptx->apb_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) reset_control_deassert(hdptx->cmn_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) reset_control_deassert(hdptx->init_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) ret = rockchip_hdptx_phy_clk_register(hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) goto err_regsmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) platform_set_drvdata(pdev, hdptx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) dev_info(dev, "hdptx phy init success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) err_regsmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) clk_bulk_unprepare(hdptx->nr_clks, hdptx->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) static struct platform_driver rockchip_hdptx_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .probe = rockchip_hdptx_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .name = "rockchip-hdptx-phy-hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .of_match_table = of_match_ptr(rockchip_hdptx_phy_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) module_platform_driver(rockchip_hdptx_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) MODULE_DESCRIPTION("Samsung HDMI-DP Transmitter Combphy Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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