Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Rockchip Samsung mipi dcphy driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _PHY_ROCKCHIP_SAMSUNG_DCPHY_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _PHY_ROCKCHIP_SAMSUNG_DCPHY_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MAX_NUM_CSI2_DPHY	(0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct samsung_mipi_dcphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	struct regmap *grf_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	struct reset_control *m_phy_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct reset_control *s_phy_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct reset_control *apb_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	struct reset_control *grf_apb_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	atomic_t stream_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	int dphy_dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	bool c_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	unsigned int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		unsigned long long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		u8 prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		u16 fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		long dsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		u8 scaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		bool ssc_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		u8 mfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		u8 mrr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	} pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif