Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Rockchip PCIe PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2016 ROCKCHIP, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * The higher 16-bit of this register is used for write protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define HIWORD_UPDATE(val, mask, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		((val) << (shift) | (mask) << ((shift) + 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PHY_MAX_LANE_NUM      4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PHY_CFG_DATA_SHIFT    7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PHY_CFG_ADDR_SHIFT    1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PHY_CFG_DATA_MASK     0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PHY_CFG_ADDR_MASK     0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PHY_CFG_RD_MASK       0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PHY_CFG_WR_ENABLE     1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PHY_CFG_WR_DISABLE    1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PHY_CFG_WR_SHIFT      0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PHY_CFG_WR_MASK       1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PHY_CFG_PLL_LOCK      0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PHY_CFG_CLK_TEST      0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PHY_CFG_CLK_SCC       0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PHY_CFG_SEPE_RATE     BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PHY_CFG_PLL_100M      BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PHY_PLL_LOCKED        BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PHY_PLL_OUTPUT        BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PHY_LANE_A_STATUS     0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PHY_LANE_B_STATUS     0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PHY_LANE_C_STATUS     0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PHY_LANE_D_STATUS     0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PHY_LANE_RX_DET_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PHY_LANE_RX_DET_TH    0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PHY_LANE_IDLE_OFF     0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PHY_LANE_IDLE_MASK    0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PHY_LANE_IDLE_A_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PHY_LANE_IDLE_B_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PHY_LANE_IDLE_C_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PHY_LANE_IDLE_D_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) struct rockchip_pcie_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned int pcie_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned int pcie_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	unsigned int pcie_laneoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) struct rockchip_pcie_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct rockchip_pcie_data *phy_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct regmap *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct phy_pcie_instance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	} phys[PHY_MAX_LANE_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct mutex pcie_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct reset_control *phy_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct clk *clk_pciephy_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	int pwr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	int init_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return container_of(inst, struct rockchip_pcie_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 					phys[inst->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 					      struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (args->args_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return rk_phy->phys[0].phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return rk_phy->phys[args->args[0]].phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			      u32 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		     HIWORD_UPDATE(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				   PHY_CFG_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				   PHY_CFG_DATA_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		     HIWORD_UPDATE(addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				   PHY_CFG_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				   PHY_CFG_ADDR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		     HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				   PHY_CFG_WR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				   PHY_CFG_WR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		     HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				   PHY_CFG_WR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 				   PHY_CFG_WR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			     u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		     HIWORD_UPDATE(addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				   PHY_CFG_RD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				   PHY_CFG_ADDR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	regmap_read(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		    rk_phy->phy_data->pcie_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		    &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int rockchip_pcie_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	mutex_lock(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	regmap_write(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		     rk_phy->phy_data->pcie_laneoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		     HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				   PHY_LANE_IDLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				   PHY_LANE_IDLE_A_SHIFT + inst->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (--rk_phy->pwr_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	err = reset_control_assert(rk_phy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		dev_err(&phy->dev, "assert phy_rst err %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		goto err_restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	mutex_unlock(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) err_restore:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	rk_phy->pwr_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	regmap_write(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		     rk_phy->phy_data->pcie_laneoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				   PHY_LANE_IDLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				   PHY_LANE_IDLE_A_SHIFT + inst->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	mutex_unlock(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int rockchip_pcie_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	mutex_lock(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	regmap_write(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		     rk_phy->phy_data->pcie_laneoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				   PHY_LANE_IDLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				   PHY_LANE_IDLE_A_SHIFT + inst->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (rk_phy->pwr_cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	err = reset_control_deassert(rk_phy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		dev_err(&phy->dev, "deassert phy_rst err %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		goto err_pwr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		     HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				   PHY_CFG_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				   PHY_CFG_ADDR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 * No documented timeout value for phy operation below,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	 * so we make it large enough here. And we use loop-break
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * method which should not be harmful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		regmap_read(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			    rk_phy->phy_data->pcie_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			    &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		if (status & PHY_PLL_LOCKED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			dev_dbg(&phy->dev, "pll locked!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		dev_err(&phy->dev, "pll lock timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		goto err_pll_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		regmap_read(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			    rk_phy->phy_data->pcie_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			    &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		if (!(status & PHY_PLL_OUTPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			dev_dbg(&phy->dev, "pll output enable done!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		dev_err(&phy->dev, "pll output enable timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		goto err_pll_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		     HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				   PHY_CFG_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				   PHY_CFG_ADDR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		regmap_read(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			    rk_phy->phy_data->pcie_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			    &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		if (status & PHY_PLL_LOCKED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			dev_dbg(&phy->dev, "pll relocked!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		dev_err(&phy->dev, "pll relock timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		goto err_pll_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	mutex_unlock(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) err_pll_lock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	reset_control_assert(rk_phy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) err_pwr_cnt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	rk_phy->pwr_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	mutex_unlock(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int rockchip_pcie_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	mutex_lock(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (rk_phy->init_cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	err = clk_prepare_enable(rk_phy->clk_pciephy_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		dev_err(&phy->dev, "Fail to enable pcie ref clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		goto err_refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	err = reset_control_assert(rk_phy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		dev_err(&phy->dev, "assert phy_rst err %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		goto err_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	mutex_unlock(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) err_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	clk_disable_unprepare(rk_phy->clk_pciephy_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) err_refclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	rk_phy->init_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	mutex_unlock(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int rockchip_pcie_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	mutex_lock(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (--rk_phy->init_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		goto err_init_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	clk_disable_unprepare(rk_phy->clk_pciephy_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) err_init_cnt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	mutex_unlock(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct phy_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.init		= rockchip_pcie_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.exit		= rockchip_pcie_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.power_on	= rockchip_pcie_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.power_off	= rockchip_pcie_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct rockchip_pcie_data rk3399_pcie_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.pcie_conf = 0xe220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.pcie_status = 0xe2a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.pcie_laneoff = 0xe214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct of_device_id rockchip_pcie_phy_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.compatible = "rockchip,rk3399-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.data = &rk3399_pcie_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int rockchip_pcie_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct rockchip_pcie_phy *rk_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	u32 phy_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	grf = syscon_node_to_regmap(dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		dev_err(dev, "Cannot find GRF syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		return PTR_ERR(grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (!rk_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	of_id = of_match_device(rockchip_pcie_phy_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	rk_phy->phy_data = (struct rockchip_pcie_data *)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	rk_phy->reg_base = grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	mutex_init(&rk_phy->pcie_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	rk_phy->phy_rst = devm_reset_control_get(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (IS_ERR(rk_phy->phy_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 			dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 				"missing phy property for reset controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		return PTR_ERR(rk_phy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	if (IS_ERR(rk_phy->clk_pciephy_ref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		dev_err(dev, "refclk not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		return PTR_ERR(rk_phy->clk_pciephy_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	/* parse #phy-cells to see if it's legacy PHY model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	dev_dbg(dev, "phy number is %d\n", phy_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	for (i = 0; i < phy_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		if (IS_ERR(rk_phy->phys[i].phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 			dev_err(dev, "failed to create PHY%d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			return PTR_ERR(rk_phy->phys[i].phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		rk_phy->phys[i].index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	platform_set_drvdata(pdev, rk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	phy_provider = devm_of_phy_provider_register(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 					rockchip_pcie_phy_of_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct platform_driver rockchip_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	.probe		= rockchip_pcie_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		.name	= "rockchip-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		.of_match_table = rockchip_pcie_phy_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) module_platform_driver(rockchip_pcie_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MODULE_DESCRIPTION("Rockchip PCIe PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_LICENSE("GPL v2");