^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip USB2.0 PHY with Naneng IP block driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/extcon-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/power_supply.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/usb/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/wakelock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct rockchip_usb2phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BIT_WRITEABLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OTG_SCHEDULE_DELAY (1 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum rockchip_usb2phy_port_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) USB2PHY_PORT_OTG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) USB2PHY_PORT_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) USB2PHY_NUM_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum calibrate_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SWING_CALIBRATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CURRENT_COMPENSATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CALIBRATION_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const unsigned int rockchip_usb2phy_extcon_cable[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) EXTCON_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) EXTCON_USB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) EXTCON_USB_VBUS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) EXTCON_CHG_USB_SDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) EXTCON_CHG_USB_CDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) EXTCON_CHG_USB_DCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) EXTCON_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct usb2phy_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int bitend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int bitstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * struct rockchip_chg_det_reg: usb charger detect registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @chg_en: charge detector enable signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @chg_rst: charge detector reset signal, active high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @chg_valid: charge valid signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @phy_connect: PHY start handshake signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct rockchip_chg_det_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct usb2phy_reg chg_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct usb2phy_reg chg_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct usb2phy_reg chg_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct usb2phy_reg phy_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * struct rockchip_usb2phy_port_cfg: usb phy port configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @bypass_otgsuspendm: otg-suspendm bypass control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 0: iddig; 1: grf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @bvalidfall_det_en: vbus valid fall detection enable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @bvalidfall_det_st: vbus valid fall detection status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @bvalidfall_det_clr: vbus valid fall detection clear register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @bvalidrise_det_en: vbus valid rise detection enable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @bvalidrise_det_st: vbus valid rise detection status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @bvalidrise_det_clr: vbus valid rise detection clear register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @disconfall_det_en: host connect detection enable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @disconfall_det_st: host connect detection status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @disconfall_det_clr: host connect detection clear register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @disconrise_det_en: host disconnect detection enable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @disconrise_det_st: host disconnect detection status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @disconrise_det_clr: host disconnect detection clear register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @idfall_det_en: id fall detection enable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @idfall_det_st: id fall detection state register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @idfall_det_clr: id fall detection clear register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @idpullup: id pin pullup or pulldown control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @iddig_output: utmi iddig value from grf output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @iddig_en: select utmi iddig output from grf or phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 0: from phy output; 1: from grf output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @idrise_det_en: id rise detection enable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @idrise_det_st: id rise detection state register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @idrise_det_clr: id rise detection clear register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @ls_det_en: linestate detection enable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @ls_det_st: linestate detection state register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @ls_det_clr: linestate detection clear register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @phy_sus: phy suspend register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @utmi_bvalid: utmi vbus bvalid status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @utmi_iddig: otg port id pin status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @utmi_hostdet: utmi host disconnect status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct rockchip_usb2phy_port_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct usb2phy_reg bypass_otgsuspendm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct usb2phy_reg bvalidfall_det_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct usb2phy_reg bvalidfall_det_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct usb2phy_reg bvalidfall_det_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct usb2phy_reg bvalidrise_det_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct usb2phy_reg bvalidrise_det_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct usb2phy_reg bvalidrise_det_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct usb2phy_reg disconfall_det_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct usb2phy_reg disconfall_det_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct usb2phy_reg disconfall_det_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct usb2phy_reg disconrise_det_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct usb2phy_reg disconrise_det_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct usb2phy_reg disconrise_det_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct usb2phy_reg idfall_det_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct usb2phy_reg idfall_det_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct usb2phy_reg idfall_det_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct usb2phy_reg idpullup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct usb2phy_reg iddig_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct usb2phy_reg iddig_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct usb2phy_reg idrise_det_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct usb2phy_reg idrise_det_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct usb2phy_reg idrise_det_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct usb2phy_reg ls_det_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct usb2phy_reg ls_det_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct usb2phy_reg ls_det_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct usb2phy_reg phy_sus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct usb2phy_reg utmi_bvalid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct usb2phy_reg utmi_iddig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct usb2phy_reg utmi_hostdet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * struct rockchip_usb2phy_cfg: usb phy configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @reg: the address offset of grf for usb-phy config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @num_ports: specify how many ports that the phy has.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @clks: array of input clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @num_clks: number of input clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @phy_tuning: phy default parameters tuning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @phy_lowpower: phy low power mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @clkout_ctl: keep on/turn off output clk of phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @port_cfgs: ports register configuration, assigned by driver data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @chg_det: charger detection registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @last: indicate the last one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct rockchip_usb2phy_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int (*phy_tuning)(struct rockchip_usb2phy *rphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int (*phy_lowpower)(struct rockchip_usb2phy *rphy, bool en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct usb2phy_reg clkout_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const struct rockchip_chg_det_reg chg_det;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bool last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * struct rockchip_usb2phy_port: usb phy port data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @phy: the struct phy of this port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @port_id: flag for otg port or host port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @perip_connected: flag for periphyeral connect status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @prev_iddig: previous otg port id pin status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @suspended: phy suspended flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @vbus_attached: otg device vbus status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @vbus_always_on: otg vbus is always powered on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @vbus_enabled: vbus regulator status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @ls_irq: IRQ number assigned for linestate detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @disconnect_irq: IRQ number assigned for host disconnect detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @id_irq: IRQ number assigned for id fall or rise detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @mutex: for register updating in interrupt thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @otg_sm_work: OTG periphreal connect or disconnect judgement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @vbus: vbus regulator supply on few rockchip boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @port_cfg: port register configuration, assigned by driver data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @wakelock: wakeup source for otg-port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @mode: the dr_mode of the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct rockchip_usb2phy_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bool perip_connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) bool prev_iddig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bool suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) bool vbus_attached;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bool vbus_always_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) bool vbus_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int bvalid_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ls_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int disconnect_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int id_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct mutex mutex; /* protects register of phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct delayed_work otg_sm_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct regulator *vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const struct rockchip_usb2phy_port_cfg *port_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct wake_lock wakelock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) enum usb_dr_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * struct rockchip_usb2phy: usb2.0 phy driver data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @dev: pointer to our struct device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @grf: General Register Files regmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @base: the base address of APB interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @reset: power reset signal for phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @clks: array of input clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @num_clks: number of input clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @clk480m: clock struct of phy output clk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @clk480m_hw: clock struct of phy output clk management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @chg_type: USB charger types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @edev_self: represent the source of extcon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @edev: extcon device for notification registration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @vup_gpio: gpio switch for pull-up register on DM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @wait_timer: hrtimer for phy calibration delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @cal_state: state of phy calibration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @phy_cfg: phy register configuration, assigned by driver data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @ports: phy port instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct rockchip_usb2phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct clk *clk480m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct clk_hw clk480m_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) enum power_supply_type chg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) bool edev_self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct extcon_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct gpio_desc *vup_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct hrtimer wait_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) enum calibrate_state cal_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) const struct rockchip_usb2phy_cfg *phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static inline int property_enable(struct regmap *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) const struct usb2phy_reg *reg, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int val, mask, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) tmp = en ? reg->enable : reg->disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mask = GENMASK(reg->bitend, reg->bitstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return regmap_write(base, reg->offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static inline bool property_enabled(struct regmap *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) const struct usb2phy_reg *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int tmp, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = regmap_read(base, reg->offset, &orig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) tmp = (orig & mask) >> reg->bitstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return tmp == reg->enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct rockchip_usb2phy *rphy =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) container_of(hw, struct rockchip_usb2phy, clk480m_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* turn on 480m clk output if it is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* waiting for the clk become stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) usleep_range(500, 600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct rockchip_usb2phy *rphy =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) container_of(hw, struct rockchip_usb2phy, clk480m_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* turn off 480m clk output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct rockchip_usb2phy *rphy =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) container_of(hw, struct rockchip_usb2phy, clk480m_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 480000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct clk_ops rockchip_usb2phy_clkout_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .prepare = rockchip_usb2phy_clk480m_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .unprepare = rockchip_usb2phy_clk480m_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .is_prepared = rockchip_usb2phy_clk480m_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void rockchip_usb2phy_clk480m_unregister(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct rockchip_usb2phy *rphy = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) of_clk_del_provider(rphy->dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) clk_unregister(rphy->clk480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct device_node *node = rphy->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct clk *refclk = of_clk_get_by_name(node, "phyclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) init.name = "clk_usbphy_480m";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) init.ops = &rockchip_usb2phy_clkout_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* optional override of the clockname */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) of_property_read_string(node, "clock-output-names", &init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!IS_ERR(refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) clk_name = __clk_get_name(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) init.parent_names = &clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) rphy->clk480m_hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* register the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (IS_ERR(rphy->clk480m)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = PTR_ERR(rphy->clk480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto err_clk_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) rphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto err_unreg_action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) err_unreg_action:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) of_clk_del_provider(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) err_clk_provider:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) clk_unregister(rphy->clk480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) err_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* The caller must hold rport->mutex lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int rockchip_usb2phy_enable_id_irq(struct rockchip_usb2phy *rphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct rockchip_usb2phy_port *rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = property_enable(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) &rport->port_cfg->idfall_det_clr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = property_enable(rphy->grf, &rport->port_cfg->idfall_det_en, en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = property_enable(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) &rport->port_cfg->idrise_det_clr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = property_enable(rphy->grf, &rport->port_cfg->idrise_det_en, en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* The caller must hold rport->mutex lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int rockchip_usb2phy_enable_vbus_irq(struct rockchip_usb2phy *rphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct rockchip_usb2phy_port *rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = property_enable(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) &rport->port_cfg->bvalidfall_det_clr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = property_enable(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &rport->port_cfg->bvalidfall_det_en, en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = property_enable(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) &rport->port_cfg->bvalidrise_det_clr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = property_enable(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) &rport->port_cfg->bvalidrise_det_en, en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int rockchip_usb2phy_enable_line_irq(struct rockchip_usb2phy *rphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct rockchip_usb2phy_port *rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = property_enable(rphy->grf, &rport->port_cfg->ls_det_en, en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rockchip_usb2phy_enable_disconn_irq(struct rockchip_usb2phy *rphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct rockchip_usb2phy_port *rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = property_enable(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) &rport->port_cfg->disconrise_det_clr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = property_enable(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) &rport->port_cfg->disconrise_det_en, en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct device_node *node = rphy->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct extcon_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (of_property_read_bool(node, "extcon")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) edev = extcon_get_edev_by_phandle(rphy->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (IS_ERR(edev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (PTR_ERR(edev) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_err(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "Invalid or missing extcon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return PTR_ERR(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Initialize extcon device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) edev = devm_extcon_dev_allocate(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) rockchip_usb2phy_extcon_cable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (IS_ERR(edev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ret = devm_extcon_dev_register(rphy->dev, edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_err(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "failed to register extcon device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) rphy->edev_self = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) rphy->edev = edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int rockchip_usb2phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* clear disconnect status and enable disconnect detect irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (rport->disconnect_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = rockchip_usb2phy_enable_disconn_irq(rphy, rport, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_err(rphy->dev, "failed to enable disconnect irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* clear linstate status and enable linestate detect irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (rport->ls_irq > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) (rport->port_id == USB2PHY_PORT_HOST ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) rport->mode == USB_DR_MODE_HOST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = rockchip_usb2phy_enable_line_irq(rphy, rport, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(rphy->dev, "failed to enable linestate irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* clear bvalid status and enable bvalid detect irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (rport->bvalid_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = rockchip_usb2phy_enable_vbus_irq(rphy, rport, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "failed to enable bvalid irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) rport->vbus_attached =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) property_enabled(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &rport->port_cfg->utmi_bvalid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* clear id status and enable id detect irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (rport->id_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = rockchip_usb2phy_enable_id_irq(rphy, rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev_err(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "failed to enable id irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int rockchip_usb2phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_dbg(&rport->phy->dev, "port power on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!rport->suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* waiting for the utmi_clk to become stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) usleep_range(2500, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) rport->suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int rockchip_usb2phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dev_dbg(&rport->phy->dev, "port power off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (rport->suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rport->suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static int rockchip_usb2phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int rockchip_set_vbus_power(struct rockchip_usb2phy_port *rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!rport->vbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (en && !rport->vbus_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = regulator_enable(rport->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_err(&rport->phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "Failed to enable VBUS supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) } else if (!en && rport->vbus_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ret = regulator_disable(rport->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) rport->vbus_enabled = en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int rockchip_usb2phy_set_mode(struct phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) enum phy_mode mode, int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (rport->port_id != USB2PHY_PORT_OTG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) case PHY_MODE_USB_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* fallthrough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case PHY_MODE_USB_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Disable VBUS supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) rockchip_set_vbus_power(rport, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) extcon_set_state_sync(rphy->edev, EXTCON_USB_VBUS_EN, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case PHY_MODE_USB_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Enable VBUS supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = rockchip_set_vbus_power(rport, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_err(&rport->phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "Failed to set host mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) extcon_set_state_sync(rphy->edev, EXTCON_USB_VBUS_EN, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dev_info(&rport->phy->dev, "illegal mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static enum hrtimer_restart rv1126_wait_timer_fn(struct hrtimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) enum hrtimer_restart ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ktime_t delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct rockchip_usb2phy *rphy = container_of(t, struct rockchip_usb2phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) wait_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) switch (rphy->cal_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case SWING_CALIBRATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* disable tx swing calibrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) writel(0x5d, rphy->base + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* read the value of rsistance calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) reg = readl(rphy->base + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* open the pull-up resistor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) gpiod_set_value(rphy->vup_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* set cfg_hs_strg 0 to increase chirpk amplitude */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) writel(0x08, rphy->base + 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * set internal 45 Ohm resistance minimal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * increase chirpk amplitude
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) writel(0x7c, rphy->base + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) delay = ktime_set(0, 1200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) hrtimer_forward_now(&rphy->wait_timer, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) rphy->cal_state = CURRENT_COMPENSATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = HRTIMER_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case CURRENT_COMPENSATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* close the pull-up resistor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) gpiod_set_value(rphy->vup_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * set cfg_sel_strength and cfg_sel_pw 1 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * correct the effect of pull-up resistor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) writel(0xe8, rphy->base + 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* write the value of rsistance calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) writel(reg, rphy->base + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) delay = ktime_set(0, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) hrtimer_forward_now(&rphy->wait_timer, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) rphy->cal_state = CALIBRATION_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = HRTIMER_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) case CALIBRATION_DONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* enable tx swing calibrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) writel(0x4d, rphy->base + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* fall through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ret = HRTIMER_NORESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static int rv1126_usb2phy_calibrate(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ktime_t delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (rport->port_id != USB2PHY_PORT_OTG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) delay = ktime_set(0, 500000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) rphy->cal_state = SWING_CALIBRATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) hrtimer_start(&rphy->wait_timer, delay, HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static struct phy_ops rockchip_usb2phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .init = rockchip_usb2phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .exit = rockchip_usb2phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .power_on = rockchip_usb2phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .power_off = rockchip_usb2phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .set_mode = rockchip_usb2phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static const char *chg_to_string(enum power_supply_type chg_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) switch (chg_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case POWER_SUPPLY_TYPE_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return "USB_SDP_CHARGER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) case POWER_SUPPLY_TYPE_USB_DCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return "USB_DCP_CHARGER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case POWER_SUPPLY_TYPE_USB_CDP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return "USB_CDP_CHARGER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return "INVALID_CHARGER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static void rockchip_chg_detect(struct rockchip_usb2phy *rphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct rockchip_usb2phy_port *rport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) bool chg_valid, phy_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) reset_control_assert(rphy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* CHG_RST is set to 1'b0 to start charge detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) for (cnt = 0; cnt < 12; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) chg_valid = property_enabled(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) &rphy->phy_cfg->chg_det.chg_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) phy_connect =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) property_enabled(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) &rphy->phy_cfg->chg_det.phy_connect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) result = (chg_valid << 1) | phy_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) switch (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) rphy->chg_type = POWER_SUPPLY_TYPE_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* fall through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_info(&rport->phy->dev, "charger = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) chg_to_string(rphy->chg_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) reset_control_deassert(rphy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* waiting for the utmi_clk to become stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) usleep_range(2500, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* disable the chg detection module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static irqreturn_t rockchip_usb2phy_disconnect_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct rockchip_usb2phy_port *rport = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!property_enabled(rphy->grf, &rport->port_cfg->disconrise_det_st))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* clear disconnect rise detect irq pending status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) property_enable(rphy->grf, &rport->port_cfg->disconrise_det_clr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* prevent fs/ls device disconnect before enumeration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (!property_enabled(rphy->grf, &rport->port_cfg->utmi_hostdet))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* enable linestate detect irq to detect next host connect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) rockchip_usb2phy_enable_line_irq(rphy, rport, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dev_dbg(&rport->phy->dev, "host disconnected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) rockchip_usb2phy_power_off(rport->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct rockchip_usb2phy_port *rport = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev_dbg(&rport->phy->dev, "linestate interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* disable linestate detect irq and clear its status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) rockchip_usb2phy_enable_line_irq(rphy, rport, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (!rport->suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (rport->port_id != USB2PHY_PORT_HOST &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) rport->mode != USB_DR_MODE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev_dbg(&rport->phy->dev, "host connected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) rockchip_usb2phy_power_on(rport->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static unsigned int cable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct rockchip_usb2phy_port *rport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) container_of(work, struct rockchip_usb2phy_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) otg_sm_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (rport->vbus_attached) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) extcon_get_state(rphy->edev, EXTCON_USB_VBUS_EN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) !property_enabled(rphy->grf, &rport->port_cfg->utmi_iddig))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (rport->perip_connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) rockchip_chg_detect(rphy, rport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) switch (rphy->chg_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) case POWER_SUPPLY_TYPE_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) wake_lock(&rport->wakelock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) cable = EXTCON_CHG_USB_SDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) rport->perip_connected = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) case POWER_SUPPLY_TYPE_USB_DCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) cable = EXTCON_CHG_USB_DCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) case POWER_SUPPLY_TYPE_USB_CDP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) wake_lock(&rport->wakelock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) cable = EXTCON_CHG_USB_CDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) rport->perip_connected = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (!rport->perip_connected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (extcon_get_state(rphy->edev, EXTCON_CHG_USB_DCP) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) extcon_set_state_sync(rphy->edev, EXTCON_CHG_USB_DCP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev_dbg(&rport->phy->dev, "usb peripheral disconnect\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) wake_unlock(&rport->wakelock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) rport->perip_connected = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) extcon_set_state(rphy->edev, cable, rport->vbus_attached);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) extcon_sync(rphy->edev, cable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (rphy->edev_self && (extcon_get_state(rphy->edev, EXTCON_USB) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) rport->perip_connected)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) extcon_set_state(rphy->edev, EXTCON_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) rport->perip_connected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) extcon_sync(rphy->edev, EXTCON_USB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) extcon_sync(rphy->edev, EXTCON_USB_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* Show & store the current value of otg mode for otg port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static ssize_t otg_mode_show(struct device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct rockchip_usb2phy *rphy = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct rockchip_usb2phy_port *rport = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) rport = &rphy->ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (rport->port_id == USB2PHY_PORT_OTG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (!rport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dev_err(rphy->dev, "Fail to get otg port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) } else if (rport->port_id != USB2PHY_PORT_OTG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_err(rphy->dev, "No support otg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) switch (rport->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) case USB_DR_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return sprintf(buf, "host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) case USB_DR_MODE_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return sprintf(buf, "peripheral\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) case USB_DR_MODE_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return sprintf(buf, "otg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) case USB_DR_MODE_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return sprintf(buf, "UNKNOWN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static ssize_t otg_mode_store(struct device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct rockchip_usb2phy *rphy = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct rockchip_usb2phy_port *rport = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) enum usb_dr_mode new_dr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) int rc = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) rport = &rphy->ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (rport->port_id == USB2PHY_PORT_OTG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (!rport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) dev_err(rphy->dev, "Fail to get otg port!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) } else if (rport->port_id != USB2PHY_PORT_OTG ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) rport->mode == USB_DR_MODE_UNKNOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dev_err(rphy->dev, "No support otg!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!strncmp(buf, "0", 1) || !strncmp(buf, "otg", 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) new_dr_mode = USB_DR_MODE_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) } else if (!strncmp(buf, "1", 1) || !strncmp(buf, "host", 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) new_dr_mode = USB_DR_MODE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) } else if (!strncmp(buf, "2", 1) || !strncmp(buf, "peripheral", 10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) new_dr_mode = USB_DR_MODE_PERIPHERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dev_err(rphy->dev, "Error mode! Input 'otg' or 'host' or 'peripheral'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (rport->mode == new_dr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dev_warn(rphy->dev, "Same as current mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) rport->mode = new_dr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) switch (rport->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) case USB_DR_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) rport->perip_connected = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) extcon_set_state(rphy->edev, EXTCON_USB, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) extcon_sync(rphy->edev, EXTCON_USB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) extcon_sync(rphy->edev, EXTCON_USB_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) property_enable(rphy->grf, &rport->port_cfg->idpullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) property_enable(rphy->grf, &rport->port_cfg->iddig_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) property_enable(rphy->grf, &rport->port_cfg->iddig_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) case USB_DR_MODE_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_DEVICE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) property_enable(rphy->grf, &rport->port_cfg->idpullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) property_enable(rphy->grf, &rport->port_cfg->iddig_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) property_enable(rphy->grf, &rport->port_cfg->iddig_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) case USB_DR_MODE_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_OTG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) property_enable(rphy->grf, &rport->port_cfg->iddig_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) property_enable(rphy->grf, &rport->port_cfg->iddig_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if ((rport->mode == USB_DR_MODE_PERIPHERAL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) rport->mode == USB_DR_MODE_OTG) && property_enabled(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) &rport->port_cfg->utmi_bvalid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) rport->vbus_attached = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) cancel_delayed_work_sync(&rport->otg_sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static DEVICE_ATTR_RW(otg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* Group all the usb2 phy attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static struct attribute *usb2_phy_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) &dev_attr_otg_mode.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static struct attribute_group usb2_phy_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .name = NULL, /* we want them in the same directory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .attrs = usb2_phy_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct rockchip_usb2phy_port *rport = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (!property_enabled(rphy->grf, &rport->port_cfg->bvalidfall_det_st) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) !property_enabled(rphy->grf, &rport->port_cfg->bvalidrise_det_st))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* clear bvalid fall or rise detect irq pending status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (property_enabled(rphy->grf, &rport->port_cfg->bvalidfall_det_st)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) property_enable(rphy->grf, &rport->port_cfg->bvalidfall_det_clr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) rport->vbus_attached = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) } else if (property_enabled(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) &rport->port_cfg->bvalidrise_det_st)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) property_enable(rphy->grf, &rport->port_cfg->bvalidrise_det_clr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) rport->vbus_attached = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) cancel_delayed_work_sync(&rport->otg_sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct rockchip_usb2phy_port *rport = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) bool cable_vbus_state = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (!property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) !property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* clear id fall or rise detect irq pending status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) property_enable(rphy->grf, &rport->port_cfg->idfall_det_clr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) cable_vbus_state = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) } else if (property_enabled(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) &rport->port_cfg->idrise_det_st)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) property_enable(rphy->grf, &rport->port_cfg->idrise_det_clr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) cable_vbus_state = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dev_dbg(&rport->phy->dev, "id %s interrupt\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) cable_vbus_state ? "fall" : "rise");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) extcon_set_state(rphy->edev, EXTCON_USB_HOST, cable_vbus_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, cable_vbus_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) extcon_sync(rphy->edev, EXTCON_USB_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) rockchip_set_vbus_power(rport, cable_vbus_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct rockchip_usb2phy_port *rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct device_node *child_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) int iddig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) mutex_init(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) rport->port_id = USB2PHY_PORT_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) rport->vbus_attached = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) rport->vbus_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) rport->prev_iddig = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) rport->vbus_always_on =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) of_property_read_bool(child_np, "rockchip,vbus-always-on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ret = rockchip_usb2phy_extcon_register(rphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* Get Vbus regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) rport->vbus = devm_regulator_get_optional(&rport->phy->dev, "vbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (IS_ERR(rport->vbus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (PTR_ERR(rport->vbus) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) dev_warn(&rport->phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) "Failed to get VBUS supply regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) rport->vbus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * The default value of bypass_otgsuspendm is 1 that we must set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * otg_suspendm and LS_PAR_EN by software when switching drd role.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * So we disable the otg_suspend_bypass to let hardware auto-switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * device mode or host mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) property_enable(rphy->grf, &rport->port_cfg->bypass_otgsuspendm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* Request linstate interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) rport->ls_irq = of_irq_get_byname(child_np, "linestate");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (rport->ls_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) dev_err(rphy->dev, "no linestate irq provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) rockchip_usb2phy_linestate_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) "rockchip_usb2phy", rport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_err(rphy->dev, "failed to request linestate irq handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (rport->mode == USB_DR_MODE_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (rphy->edev_self) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) extcon_set_state(rphy->edev, EXTCON_USB, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * Here set iddig to 0 by disable idpullup, the otg_suspendm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * will be set to 1 to enable the disconnect detection module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * and the LS_PAR_EN will be set to 1 to enable low speed device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * enumerate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) property_enable(rphy->grf, &rport->port_cfg->idpullup, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* Request disconnect interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) rport->disconnect_irq = of_irq_get_byname(child_np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) "disconnect");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (rport->disconnect_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dev_err(rphy->dev, "no disconnect irq provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ret = devm_request_threaded_irq(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) rport->disconnect_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) rockchip_usb2phy_disconnect_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) "rockchip_usb2phy", rport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) dev_err(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) "failed to request disconnect irq handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* Request otg iddig interrupt only if there is no extcon property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (rphy->edev_self) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) rport->id_irq = of_irq_get_byname(child_np, "otg-id");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (rport->id_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) dev_err(rphy->dev, "no otg id irq provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) ret = devm_request_threaded_irq(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) rport->id_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) rockchip_usb2phy_id_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) "rockchip_usb2phy_id",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) rport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dev_err(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) "failed to request otg-id irq handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) iddig = property_enabled(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) &rport->port_cfg->utmi_iddig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (!iddig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) extcon_set_state(rphy->edev, EXTCON_USB, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* Enable VBUS supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ret = rockchip_set_vbus_power(rport, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (rport->vbus_always_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* Request otg bvalid interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (rport->bvalid_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) dev_err(rphy->dev, "no vbus valid irq provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) rockchip_usb2phy_bvalid_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) "rockchip_usb2phy_bvalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) rport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) dev_err(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) "failed to request otg-bvalid irq handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * Let us put phy-port into suspend mode here for saving power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * consumption, and usb controller will resume it during probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * time if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) rport->suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) struct rockchip_usb2phy_port *rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct device_node *child_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) mutex_init(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) rport->port_id = USB2PHY_PORT_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* Request disconnect interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) rport->disconnect_irq = of_irq_get_byname(child_np, "disconnect");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (rport->disconnect_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) dev_err(rphy->dev, "no disconnect irq provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ret = devm_request_threaded_irq(rphy->dev, rport->disconnect_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) rockchip_usb2phy_disconnect_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) "rockchip_usb2phy", rport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) dev_err(rphy->dev, "failed to request disconnect irq handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* Request linstate interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) rport->ls_irq = of_irq_get_byname(child_np, "linestate");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (rport->ls_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) dev_err(rphy->dev, "no linestate irq provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) rockchip_usb2phy_linestate_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) "rockchip_usb2phy", rport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dev_err(rphy->dev, "failed to request linestate irq handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * Let us put phy-port into suspend mode here for saving power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * consumption, and usb controller will resume it during probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * time if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) rport->suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static int rockchip_usb2phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct device_node *child_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) struct rockchip_usb2phy *rphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) const struct rockchip_usb2phy_cfg *phy_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (!rphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) dev_err(dev, "missing memory resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) rphy->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (IS_ERR(rphy->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) dev_err(dev, "failed to remap phy regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return PTR_ERR(rphy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (IS_ERR(rphy->grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return PTR_ERR(rphy->grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* Get PHY power reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) rphy->reset = devm_reset_control_get(dev, "u2phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (IS_ERR(rphy->reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return PTR_ERR(rphy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) rphy->vup_gpio = devm_gpiod_get_optional(dev, "vup", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (IS_ERR(rphy->vup_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ret = PTR_ERR(rphy->vup_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) dev_err(dev, "failed to get vup gpio (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) reset_control_assert(rphy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) reset_control_deassert(rphy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) match = of_match_device(dev->driver->of_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (!match || !match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) dev_err(dev, "phy configs are not assigned!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (of_property_read_u32(np, "reg", ®)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) dev_err(dev, "the reg property is not assigned in %s node\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) rphy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) phy_cfgs = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* find out a proper config which can be matched with dt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (phy_cfgs[index].reg == reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) rphy->phy_cfg = &phy_cfgs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) } while (!phy_cfgs[index++].last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (!rphy->phy_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) dev_err(dev, "no phy-config can be matched with %s node\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) rphy->num_clks = rphy->phy_cfg->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) rphy->clks = devm_kmemdup(dev, rphy->phy_cfg->clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) rphy->num_clks * sizeof(struct clk_bulk_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (!rphy->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) ret = devm_clk_bulk_get(dev, rphy->num_clks, rphy->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) rphy->num_clks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) ret = clk_bulk_prepare_enable(rphy->num_clks, rphy->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) platform_set_drvdata(pdev, rphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (rphy->phy_cfg->phy_tuning) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) ret = rphy->phy_cfg->phy_tuning(rphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) for_each_available_child_of_node(np, child_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct rockchip_usb2phy_port *rport = &rphy->ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /* This driver aims to support both otg-port and host-port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (of_node_cmp(child_np->name, "host-port") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) of_node_cmp(child_np->name, "otg-port"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) goto next_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (rphy->vup_gpio &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) of_device_is_compatible(np, "rockchip,rv1126-usb2phy")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) rockchip_usb2phy_ops.calibrate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) rv1126_usb2phy_calibrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) hrtimer_init(&rphy->wait_timer, CLOCK_MONOTONIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) rphy->wait_timer.function = &rv1126_wait_timer_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) dev_err(dev, "failed to create phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ret = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) rport->phy = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) phy_set_drvdata(rport->phy, rport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) /* initialize otg/host port separately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (!of_node_cmp(child_np->name, "host-port")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) ret = rockchip_usb2phy_host_port_init(rphy, rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) ret = rockchip_usb2phy_otg_port_init(rphy, rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) next_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /* to prevent out of boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (++index >= rphy->phy_cfg->num_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (IS_ERR_OR_NULL(provider))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* Attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) ret = sysfs_create_group(&dev->kobj, &usb2_phy_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) dev_err(dev, "Cannot create sysfs group: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ret = rockchip_usb2phy_clk480m_register(rphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) dev_err(dev, "failed to register 480m output clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (of_property_read_bool(np, "wakeup-source"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) device_init_wakeup(rphy->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) device_init_wakeup(rphy->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) of_node_put(child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) clk_bulk_disable_unprepare(rphy->num_clks, rphy->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static int rockchip_usb2phy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct rockchip_usb2phy *rphy = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (rphy->vup_gpio &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) of_device_is_compatible(np, "rockchip,rv1126-usb2phy"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) hrtimer_cancel(&rphy->wait_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static int rv1126_usb2phy_tuning(struct rockchip_usb2phy *rphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) u32 rcal, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (rphy->phy_cfg->reg == 0xff4c0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* set iddig interrupt filter time to 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ret = regmap_write(rphy->grf, 0x1031c, 0x000f4240);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /* set pready_cnt to 1 and rden_cnt to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) ret = regmap_write(rphy->grf, 0x1027c, 0x0f0f0100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) reg = readl(rphy->base + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /* Enable Rterm self calibration and wait for rcal trim done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) writel(reg & ~BIT(2), rphy->base + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * If Rterm is disconnected, self calibration will fail and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * rcal trim done will be set in about 3.5 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (readl(rphy->base + 0x34) & BIT(4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) dev_dbg(rphy->dev, "Rterm disconnected");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ret = readl_poll_timeout(rphy->base + 0x34, rcal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) rcal & BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) 100, 600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) dev_err(rphy->dev, "Rterm calibration timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /* Use rcal out calibration code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) reg = (reg & ~(0x0f << 3)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ((rcal & 0x0f) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* Disable Rterm self calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) writel(reg | BIT(2), rphy->base + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (rphy->phy_cfg->reg == 0xff4c8000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) /* set pready_cnt to 1 and rden_cnt to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ret = regmap_write(rphy->grf, 0x1028c, 0x0f0f0100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) /* Enable host port wakeup irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ret = regmap_write(rphy->grf, 0x0000, 0x00040004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) static int rv1126_usb2phy_low_power(struct rockchip_usb2phy *rphy, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) reg = readl(rphy->base + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) /* bypass or enable bc detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) reg = en ? reg | BIT(5) : reg & ~BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) writel(reg, rphy->base + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static const struct clk_bulk_data rv1126_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) { .id = "phyclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) { .id = "pclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static int rockchip_usb2phy_pm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) struct rockchip_usb2phy_port *rport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) bool wakeup_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (device_may_wakeup(rphy->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) wakeup_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) rport = &rphy->ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (!rport->phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (rport->port_id == USB2PHY_PORT_OTG &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) rport->id_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) rport->prev_iddig =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) property_enabled(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) &rport->port_cfg->utmi_iddig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) ret = rockchip_usb2phy_enable_id_irq(rphy, rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) dev_err(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) "failed to disable id irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (rport->port_id == USB2PHY_PORT_OTG && wakeup_enable &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) rport->bvalid_irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) enable_irq_wake(rport->bvalid_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* activate the linestate to detect the remove wakeup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) ret = rockchip_usb2phy_enable_line_irq(rphy, rport, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) dev_err(rphy->dev, "failed to enable linestate irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (wakeup_enable && rport->ls_irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) enable_irq_wake(rport->ls_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) /* enter low power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (rphy->phy_cfg->phy_lowpower)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) ret = rphy->phy_cfg->phy_lowpower(rphy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static int rockchip_usb2phy_pm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) struct rockchip_usb2phy_port *rport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) bool iddig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) bool wakeup_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if (device_may_wakeup(rphy->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) wakeup_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* exit low power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (rphy->phy_cfg->phy_lowpower)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ret = rphy->phy_cfg->phy_lowpower(rphy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) rport = &rphy->ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (!rport->phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (rport->port_id == USB2PHY_PORT_OTG &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) rport->id_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) mutex_lock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) iddig = property_enabled(rphy->grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) &rport->port_cfg->utmi_iddig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) ret = rockchip_usb2phy_enable_id_irq(rphy, rport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) mutex_unlock(&rport->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) dev_err(rphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) "failed to enable id irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (iddig != rport->prev_iddig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) dev_dbg(&rport->phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) "iddig changed during resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) rport->prev_iddig = iddig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) extcon_set_state_sync(rphy->edev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) EXTCON_USB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) !iddig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) extcon_set_state_sync(rphy->edev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) EXTCON_USB_VBUS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) !iddig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) ret = rockchip_set_vbus_power(rport, !iddig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (rport->port_id == USB2PHY_PORT_OTG && wakeup_enable &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) rport->bvalid_irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) disable_irq_wake(rport->bvalid_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (wakeup_enable && rport->ls_irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) disable_irq_wake(rport->ls_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static const struct dev_pm_ops rockchip_usb2phy_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) SET_SYSTEM_SLEEP_PM_OPS(rockchip_usb2phy_pm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) rockchip_usb2phy_pm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define ROCKCHIP_USB2PHY_DEV_PM (&rockchip_usb2phy_dev_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #define ROCKCHIP_USB2PHY_DEV_PM NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) static const struct rockchip_usb2phy_cfg rv1126_phy_cfgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .reg = 0xff4c0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .num_ports = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .phy_tuning = rv1126_usb2phy_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .phy_lowpower = rv1126_usb2phy_low_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .num_clks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .clks = rv1126_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .clkout_ctl = { 0x10230, 14, 14, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .port_cfgs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) [USB2PHY_PORT_OTG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .bypass_otgsuspendm = { 0x10234, 12, 12, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .bvalidfall_det_en = { 0x10300, 3, 3, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .bvalidfall_det_st = { 0x10304, 3, 3, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .bvalidfall_det_clr = { 0x10308, 3, 3, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .bvalidrise_det_en = { 0x10300, 2, 2, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .bvalidrise_det_st = { 0x10304, 2, 2, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .bvalidrise_det_clr = { 0x10308, 2, 2, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .disconfall_det_en = { 0x10300, 7, 7, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .disconfall_det_st = { 0x10304, 7, 7, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .disconfall_det_clr = { 0x10308, 7, 7, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .disconrise_det_en = { 0x10300, 6, 6, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .disconrise_det_st = { 0x10304, 6, 6, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .disconrise_det_clr = { 0x10308, 6, 6, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .idfall_det_en = { 0x10300, 5, 5, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .idfall_det_st = { 0x10304, 5, 5, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .idfall_det_clr = { 0x10308, 5, 5, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .idpullup = { 0x10230, 11, 11, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .iddig_output = { 0x10230, 10, 10, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .iddig_en = { 0x10230, 9, 9, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .idrise_det_en = { 0x10300, 4, 4, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .idrise_det_st = { 0x10304, 4, 4, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .idrise_det_clr = { 0x10308, 4, 4, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .ls_det_en = { 0x10300, 0, 0, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .ls_det_st = { 0x10304, 0, 0, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .ls_det_clr = { 0x10308, 0, 0, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .phy_sus = { 0x10230, 8, 0, 0x052, 0x1d5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .utmi_bvalid = { 0x10248, 9, 9, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .utmi_iddig = { 0x10248, 6, 6, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .utmi_hostdet = { 0x10248, 7, 7, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .chg_det = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .chg_en = { 0x10234, 14, 14, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .chg_rst = { 0x10234, 15, 15, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .chg_valid = { 0x10248, 12, 12, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .phy_connect = { 0x10248, 13, 13, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .reg = 0xff4c8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .num_ports = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .phy_tuning = rv1126_usb2phy_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .phy_lowpower = rv1126_usb2phy_low_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .num_clks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .clks = rv1126_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .clkout_ctl = { 0x10238, 9, 9, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .port_cfgs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) [USB2PHY_PORT_HOST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .disconfall_det_en = { 0x10300, 9, 9, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .disconfall_det_st = { 0x10304, 9, 9, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .disconfall_det_clr = { 0x10308, 9, 9, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .disconrise_det_en = { 0x10300, 8, 8, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .disconrise_det_st = { 0x10304, 8, 8, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .disconrise_det_clr = { 0x10308, 8, 8, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .ls_det_en = { 0x10300, 1, 1, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .ls_det_st = { 0x10304, 1, 1, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .ls_det_clr = { 0x10308, 1, 1, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .phy_sus = { 0x10238, 3, 0, 0x2, 0x5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .utmi_hostdet = { 0x10248, 23, 23, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .chg_det = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .chg_en = { 0x10238, 7, 7, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .chg_rst = { 0x10238, 8, 8, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .chg_valid = { 0x10248, 28, 28, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .phy_connect = { 0x10248, 29, 29, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .last = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static const struct of_device_id rockchip_usb2phy_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) { .compatible = "rockchip,rv1126-usb2phy", .data = &rv1126_phy_cfgs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) static struct platform_driver rockchip_usb2phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .probe = rockchip_usb2phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .remove = rockchip_usb2phy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .name = "rockchip-usb2phy-naneng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .pm = ROCKCHIP_USB2PHY_DEV_PM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .of_match_table = rockchip_usb2phy_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) module_platform_driver(rockchip_usb2phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) MODULE_AUTHOR("Jianing Ren <jianing.ren@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) MODULE_DESCRIPTION("Rockchip USB2.0 Naneng PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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