^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Wyon Bi <bivvy.bi@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EDP_PHY_GRF_CON0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EDP_PHY_TX_IDLE GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EDP_PHY_TX_PD GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EDP_PHY_IDDQ_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EDP_PHY_PD_PLL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EDP_PHY_GRF_CON1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EDP_PHY_PLL_DIV GENMASK(14, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EDP_PHY_GRF_CON2 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EDP_PHY_TX_RTERM GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EDP_PHY_RATE GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EDP_PHY_REF_DIV GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EDP_PHY_GRF_CON3 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EDP_PHY_TX3_EMP GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EDP_PHY_TX2_EMP GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EDP_PHY_TX1_EMP GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EDP_PHY_TX0_EMP GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EDP_PHY_GRF_CON4 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EDP_PHY_TX3_AMP GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EDP_PHY_TX2_AMP GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EDP_PHY_TX1_AMP GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EDP_PHY_TX0_AMP GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EDP_PHY_GRF_CON5 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EDP_PHY_TX_MODE GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EDP_PHY_TX3_AMP_SCALE GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EDP_PHY_TX2_AMP_SCALE GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EDP_PHY_TX1_AMP_SCALE GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EDP_PHY_TX0_AMP_SCALE GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EDP_PHY_GRF_CON6 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EDP_PHY_SSC_DEPTH GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EDP_PHY_SSC_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EDP_PHY_SSC_CNT GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EDP_PHY_GRF_CON7 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EDP_PHY_GRF_CON8 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EDP_PHY_PLL_CTL_H GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EDP_PHY_GRF_CON9 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EDP_PHY_TX_CTL GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EDP_PHY_GRF_CON10 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EDP_PHY_AUX_RCV_PD_SEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EDP_PHY_AUX_DRV_PD_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EDP_PHY_AUX_IDLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EDP_PHY_AUX_RCV_PD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EDP_PHY_AUX_DRV_PD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EDP_PHY_GRF_CON11 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EDP_PHY_AUX_RCV_VCM GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EDP_PHY_AUX_MODE GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EDP_PHY_AUX_AMP_SCALE GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EDP_PHY_AUX_AMP GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EDP_PHY_AUX_RTERM GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EDP_PHY_GRF_STATUS0 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PLL_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EDP_PHY_GRF_STATUS1 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct rockchip_edp_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk *refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline int rockchip_grf_write(struct regmap *grf, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int mask, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return regmap_write(grf, reg, (mask << 16) | (val & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int amp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int amp_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int emp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) } vp[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { {0x1, 0x1, 0x0}, {0x2, 0x1, 0x4}, {0x3, 0x1, 0x8}, {0x4, 0x1, 0xd} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { {0x3, 0x1, 0x0}, {0x5, 0x1, 0x7}, {0x6, 0x1, 0x6}, { -1, -1, -1} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { {0x5, 0x1, 0x0}, {0x7, 0x1, 0x4}, { -1, -1, -1}, { -1, -1, -1} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { {0x7, 0x1, 0x0}, { -1, -1, -1}, { -1, -1, -1}, { -1, -1, -1} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void rockchip_edp_phy_set_voltage(struct rockchip_edp_phy *edpphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct phy_configure_opts_dp *dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 amp, amp_scale, emp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) amp = vp[dp->voltage[lane]][dp->pre[lane]].amp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) amp_scale = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) emp = vp[dp->voltage[lane]][dp->pre[lane]].emp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) switch (lane) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) EDP_PHY_TX0_EMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FIELD_PREP(EDP_PHY_TX0_EMP, emp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) EDP_PHY_TX0_AMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FIELD_PREP(EDP_PHY_TX0_AMP, amp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) EDP_PHY_TX0_AMP_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) FIELD_PREP(EDP_PHY_TX0_AMP_SCALE, amp_scale));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) EDP_PHY_TX1_EMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) FIELD_PREP(EDP_PHY_TX1_EMP, emp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EDP_PHY_TX1_AMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FIELD_PREP(EDP_PHY_TX1_AMP, amp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) EDP_PHY_TX1_AMP_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FIELD_PREP(EDP_PHY_TX1_AMP_SCALE, amp_scale));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) EDP_PHY_TX2_EMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FIELD_PREP(EDP_PHY_TX2_EMP, emp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) EDP_PHY_TX2_AMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) FIELD_PREP(EDP_PHY_TX2_AMP, amp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) EDP_PHY_TX2_AMP_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FIELD_PREP(EDP_PHY_TX2_AMP_SCALE, amp_scale));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) EDP_PHY_TX3_EMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FIELD_PREP(EDP_PHY_TX3_EMP, emp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) EDP_PHY_TX3_AMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FIELD_PREP(EDP_PHY_TX3_AMP, amp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EDP_PHY_TX3_AMP_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FIELD_PREP(EDP_PHY_TX3_AMP_SCALE, amp_scale));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int rockchip_edp_phy_set_voltages(struct rockchip_edp_phy *edpphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) for (lane = 0; lane < dp->lanes; lane++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rockchip_edp_phy_set_voltage(edpphy, dp, lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int rockchip_edp_phy_set_rate(struct rockchip_edp_phy *edpphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) EDP_PHY_TX_IDLE | EDP_PHY_TX_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) FIELD_PREP(EDP_PHY_TX_IDLE, 0xf) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) FIELD_PREP(EDP_PHY_TX_PD, 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) usleep_range(100, 101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) FIELD_PREP(EDP_PHY_TX_MODE, 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) FIELD_PREP(EDP_PHY_PD_PLL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) switch (dp->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) EDP_PHY_PLL_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) FIELD_PREP(EDP_PHY_PLL_DIV, 0x4380));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) EDP_PHY_TX_RTERM | EDP_PHY_RATE | EDP_PHY_REF_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) FIELD_PREP(EDP_PHY_TX_RTERM, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) FIELD_PREP(EDP_PHY_RATE, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) FIELD_PREP(EDP_PHY_REF_DIV, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) EDP_PHY_PLL_CTL_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) FIELD_PREP(EDP_PHY_PLL_CTL_H, 0x0800));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) EDP_PHY_TX_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) FIELD_PREP(EDP_PHY_TX_CTL, 0x0000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) EDP_PHY_PLL_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) FIELD_PREP(EDP_PHY_PLL_DIV, 0x3840));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) EDP_PHY_TX_RTERM | EDP_PHY_RATE | EDP_PHY_REF_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) FIELD_PREP(EDP_PHY_TX_RTERM, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) FIELD_PREP(EDP_PHY_RATE, 0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) FIELD_PREP(EDP_PHY_REF_DIV, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) EDP_PHY_PLL_CTL_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) FIELD_PREP(EDP_PHY_PLL_CTL_H, 0x0800));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) EDP_PHY_TX_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) FIELD_PREP(EDP_PHY_TX_CTL, 0x0000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (dp->ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) EDP_PHY_SSC_DEPTH | EDP_PHY_SSC_EN | EDP_PHY_SSC_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) FIELD_PREP(EDP_PHY_SSC_DEPTH, 0x9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) FIELD_PREP(EDP_PHY_SSC_EN, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) FIELD_PREP(EDP_PHY_SSC_CNT, 0x17d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) EDP_PHY_SSC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) FIELD_PREP(EDP_PHY_SSC_EN, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) FIELD_PREP(EDP_PHY_PD_PLL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_TX_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) FIELD_PREP(EDP_PHY_TX_PD, ~GENMASK(dp->lanes - 1, 0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = regmap_read_poll_timeout(edpphy->grf, EDP_PHY_GRF_STATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) value, value & PLL_RDY, 100, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(edpphy->dev, "pll is not ready: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) FIELD_PREP(EDP_PHY_TX_MODE, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_TX_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) FIELD_PREP(EDP_PHY_TX_IDLE, ~GENMASK(dp->lanes - 1, 0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int rockchip_edp_phy_verify_config(struct rockchip_edp_phy *edpphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* If changing link rate was required, verify it's supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (dp->set_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) switch (dp->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* valid bit rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Verify lane count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) switch (dp->lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* valid lane count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * If changing voltages is required, check swing and pre-emphasis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * levels, per-lane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (dp->set_voltages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Lane count verified previously. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) for (i = 0; i < dp->lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (dp->voltage[i] > 3 || dp->pre[i] > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Sum of voltage swing and pre-emphasis levels cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * exceed 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (dp->voltage[i] + dp->pre[i] > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int rockchip_edp_phy_configure(struct phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) union phy_configure_opts *opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = rockchip_edp_phy_verify_config(edpphy, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_err(edpphy->dev, "invalid params for phy configure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (opts->dp.set_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = rockchip_edp_phy_set_rate(edpphy, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_err(edpphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "rockchip_edp_phy_set_rate failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (opts->dp.set_voltages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = rockchip_edp_phy_set_voltages(edpphy, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(edpphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "rockchip_edp_phy_set_voltages failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static bool rockchip_edp_phy_enabled(struct rockchip_edp_phy *edpphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) regmap_read(edpphy->grf, EDP_PHY_GRF_STATUS0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return FIELD_GET(PLL_RDY, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int rockchip_edp_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) clk_prepare_enable(edpphy->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (rockchip_edp_phy_enabled(edpphy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) EDP_PHY_AUX_RCV_PD | EDP_PHY_AUX_DRV_PD | EDP_PHY_AUX_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) FIELD_PREP(EDP_PHY_AUX_RCV_PD, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) FIELD_PREP(EDP_PHY_AUX_DRV_PD, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) FIELD_PREP(EDP_PHY_AUX_IDLE, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) EDP_PHY_TX_IDLE | EDP_PHY_TX_PD | EDP_PHY_PD_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) FIELD_PREP(EDP_PHY_TX_IDLE, 0xf) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) FIELD_PREP(EDP_PHY_TX_PD, 0xf) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) FIELD_PREP(EDP_PHY_PD_PLL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) usleep_range(100, 101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) EDP_PHY_AUX_RCV_VCM | EDP_PHY_AUX_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) EDP_PHY_AUX_AMP_SCALE | EDP_PHY_AUX_AMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) EDP_PHY_AUX_RTERM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) FIELD_PREP(EDP_PHY_AUX_RCV_VCM, 0x4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) FIELD_PREP(EDP_PHY_AUX_MODE, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) FIELD_PREP(EDP_PHY_AUX_AMP_SCALE, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) FIELD_PREP(EDP_PHY_AUX_AMP, 0x3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) FIELD_PREP(EDP_PHY_AUX_RTERM, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) EDP_PHY_AUX_RCV_PD | EDP_PHY_AUX_DRV_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) FIELD_PREP(EDP_PHY_AUX_RCV_PD, 0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) FIELD_PREP(EDP_PHY_AUX_DRV_PD, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) usleep_range(100, 101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) EDP_PHY_AUX_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) FIELD_PREP(EDP_PHY_AUX_IDLE, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int rockchip_edp_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) EDP_PHY_TX_IDLE | EDP_PHY_TX_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FIELD_PREP(EDP_PHY_TX_IDLE, 0xf) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FIELD_PREP(EDP_PHY_TX_PD, 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) usleep_range(100, 101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) FIELD_PREP(EDP_PHY_TX_MODE, 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) FIELD_PREP(EDP_PHY_PD_PLL, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) EDP_PHY_AUX_RCV_PD | EDP_PHY_AUX_DRV_PD | EDP_PHY_AUX_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) FIELD_PREP(EDP_PHY_AUX_RCV_PD, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) FIELD_PREP(EDP_PHY_AUX_DRV_PD, 0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) FIELD_PREP(EDP_PHY_AUX_IDLE, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) clk_disable_unprepare(edpphy->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct phy_ops rockchip_edp_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .power_on = rockchip_edp_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .power_off = rockchip_edp_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .configure = rockchip_edp_phy_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int rockchip_edp_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct rockchip_edp_phy *edpphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) edpphy = devm_kzalloc(dev, sizeof(*edpphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!edpphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) edpphy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) edpphy->grf = syscon_node_to_regmap(dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (IS_ERR(edpphy->grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = PTR_ERR(edpphy->grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_err(dev, "failed to get grf: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) edpphy->refclk = devm_clk_get(dev, "refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (IS_ERR(edpphy->refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = PTR_ERR(edpphy->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_err(dev, "failed to get refclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) phy = devm_phy_create(dev, NULL, &rockchip_edp_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(dev, "failed to create PHY: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) phy_set_drvdata(phy, edpphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_err(dev, "failed to register phy provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static const struct of_device_id rockchip_edp_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { .compatible = "rockchip,rk3568-edp-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MODULE_DEVICE_TABLE(of, rockchip_edp_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static struct platform_driver rockchip_edp_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "rockchip-edpphy-naneng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .of_match_table = of_match_ptr(rockchip_edp_phy_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .probe = rockchip_edp_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) module_platform_driver(rockchip_edp_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MODULE_DESCRIPTION("Rockchip Naneng eDP Transmitter PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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