^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip PIPE USB3.0 PCIE SATA combphy driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BIT_WRITEABLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct rockchip_combphy_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct combphy_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u16 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u16 bitend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u16 bitstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u16 disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u16 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct rockchip_combphy_grfcfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct combphy_reg pcie_mode_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct combphy_reg usb_mode_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct combphy_reg sgmii_mode_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct combphy_reg qsgmii_mode_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct combphy_reg pipe_rxterm_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct combphy_reg pipe_txelec_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct combphy_reg pipe_txcomp_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct combphy_reg pipe_clk_24m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct combphy_reg pipe_clk_25m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct combphy_reg pipe_clk_100m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct combphy_reg pipe_phymode_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct combphy_reg pipe_rate_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct combphy_reg pipe_rxterm_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct combphy_reg pipe_txelec_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct combphy_reg pipe_txcomp_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct combphy_reg pipe_clk_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct combphy_reg pipe_sel_usb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct combphy_reg pipe_sel_qsgmii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct combphy_reg pipe_phy_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct combphy_reg con0_for_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct combphy_reg con1_for_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct combphy_reg con2_for_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct combphy_reg con3_for_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct combphy_reg con0_for_sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct combphy_reg con1_for_sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct combphy_reg con2_for_sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct combphy_reg con3_for_sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct combphy_reg pipe_con0_for_sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct combphy_reg pipe_con1_for_sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct combphy_reg pipe_sgmii_mac_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct combphy_reg pipe_xpcs_phy_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct combphy_reg u3otg0_port_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct combphy_reg u3otg1_port_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct rockchip_combphy_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const struct rockchip_combphy_grfcfg *grfcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bool force_det_out; /* Tx detect Rx errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct rockchip_combphy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct regmap *pipe_grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct regmap *phy_grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct reset_control *apb_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct reset_control *phy_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const struct rockchip_combphy_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline bool param_read(struct regmap *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct combphy_reg *reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 mask, orig, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret = regmap_read(base, reg->offset, &orig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mask = GENMASK(reg->bitend, reg->bitstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) tmp = (orig & mask) >> reg->bitstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return tmp == val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int param_write(struct regmap *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const struct combphy_reg *reg, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 val, mask, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tmp = en ? reg->enable : reg->disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mask = GENMASK(reg->bitend, reg->bitstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return regmap_write(base, reg->offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mask = GENMASK(cfg->pipe_phy_status.bitend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) cfg->pipe_phy_status.bitstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val = (val & mask) >> cfg->pipe_phy_status.bitstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (priv->cfg->combphy_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = priv->cfg->combphy_cfg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(priv->dev, "failed to init phy for pcie\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (priv->cfg->force_det_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val = readl(priv->mmio + (0x19 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) writel(val, priv->mmio + (0x19 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (priv->cfg->combphy_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = priv->cfg->combphy_cfg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_err(priv->dev, "failed to init phy for usb3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (priv->cfg->combphy_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = priv->cfg->combphy_cfg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(priv->dev, "failed to init phy for sata\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (priv->cfg->combphy_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = priv->cfg->combphy_cfg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_err(priv->dev, "failed to init phy for sgmii\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) switch (priv->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case PHY_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) rockchip_combphy_pcie_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case PHY_TYPE_USB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rockchip_combphy_usb3_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case PHY_TYPE_SATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rockchip_combphy_sata_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case PHY_TYPE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case PHY_TYPE_QSGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return rockchip_combphy_sgmii_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_err(priv->dev, "incompatible PHY type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int rockchip_combphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(priv->dev, "failed to enable clks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = rockchip_combphy_set_mode(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = reset_control_deassert(priv->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (priv->mode == PHY_TYPE_USB3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) priv, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val == cfg->pipe_phy_status.enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_warn(priv->dev, "wait phy status ready timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int rockchip_combphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) reset_control_assert(priv->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct phy_ops rochchip_combphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .init = rockchip_combphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .exit = rockchip_combphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct phy *rockchip_combphy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (args->args_count != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(dev, "invalid number of arguments\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (priv->mode != PHY_NONE && priv->mode != args->args[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_warn(dev, "phy type select %d overwriting type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) args->args[0], priv->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) priv->mode = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return priv->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int rockchip_combphy_parse_dt(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct rockchip_combphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int ret, mac_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 vals[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) priv->num_clks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "rockchip,pipe-grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (IS_ERR(priv->pipe_grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return PTR_ERR(priv->pipe_grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "rockchip,pipe-phy-grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (IS_ERR(priv->phy_grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return PTR_ERR(priv->phy_grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (device_property_present(dev, "rockchip,dis-u3otg0-port"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else if (device_property_present(dev, "rockchip,dis-u3otg1-port"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) (mac_id > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (!device_property_read_u32_array(dev, "rockchip,pcie1ln-sel-bits",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) vals, ARRAY_SIZE(vals)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) regmap_write(priv->pipe_grf, vals[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) (GENMASK(vals[2], vals[1]) << 16) | (vals[3] << vals[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (IS_ERR(priv->apb_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = PTR_ERR(priv->apb_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_warn(dev, "failed to get apb reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) priv->phy_rst = devm_reset_control_get_optional(dev, "combphy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (IS_ERR(priv->phy_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = PTR_ERR(priv->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_warn(dev, "failed to get phy reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return reset_control_assert(priv->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int rockchip_combphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct rockchip_combphy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) const struct rockchip_combphy_cfg *phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) phy_cfg = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!phy_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(dev, "No OF match data provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) priv->mmio = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (IS_ERR(priv->mmio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = PTR_ERR(priv->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) priv->num_clks = phy_cfg->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) priv->clks = devm_kmemdup(dev, phy_cfg->clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) phy_cfg->num_clks * sizeof(struct clk_bulk_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!priv->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) priv->mode = PHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) priv->cfg = phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = rockchip_combphy_parse_dt(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (IS_ERR(priv->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_err(dev, "failed to create combphy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return PTR_ERR(priv->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) phy_set_drvdata(priv->phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct clk *refclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Configure PHY reference clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) for (i = 0; i < priv->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!strncmp(priv->clks[i].id, "refclk", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) refclk = priv->clks[i].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!refclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_err(priv->dev, "No refclk found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) switch (priv->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case PHY_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Set SSC downward spread spectrum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) val = readl(priv->mmio + (0x1f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val &= ~GENMASK(5, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) val |= 0x01 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) writel(val, priv->mmio + 0x7c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case PHY_TYPE_USB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Set SSC downward spread spectrum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) val = readl(priv->mmio + (0x1f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) val &= ~GENMASK(5, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) val |= 0x01 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) writel(val, priv->mmio + 0x7c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Enable adaptive CTLE for USB3.0 Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) val = readl(priv->mmio + (0x0e << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) val &= ~GENMASK(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) val |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) writel(val, priv->mmio + (0x0e << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Set PLL KVCO fine tuning signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) val = readl(priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) val &= ~(0x7 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) val |= 0x2 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) writel(val, priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Set PLL LPF R1 to su_trim[10:7]=1001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) writel(0x4, priv->mmio + (0xb << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Set PLL input clock divider 1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) val = readl(priv->mmio + (0x5 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) val &= ~(0x3 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) val |= 0x1 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) writel(val, priv->mmio + (0x5 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Set PLL loop divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) writel(0x32, priv->mmio + (0x11 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Set PLL KVCO to min and set PLL charge pump current to max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) writel(0xf0, priv->mmio + (0xa << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) param_write(priv->phy_grf, &cfg->usb_mode_set, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case PHY_TYPE_SATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) writel(0x41, priv->mmio + 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) writel(0x8F, priv->mmio + 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) param_write(priv->phy_grf, &cfg->con0_for_sata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) param_write(priv->phy_grf, &cfg->con1_for_sata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) param_write(priv->phy_grf, &cfg->con2_for_sata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) param_write(priv->phy_grf, &cfg->con3_for_sata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case PHY_TYPE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case PHY_TYPE_QSGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_err(priv->dev, "incompatible PHY type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) rate = clk_get_rate(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case 24000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) val = readl(priv->mmio + (0x0e << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) val &= ~GENMASK(7, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) val |= 0x01 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) writel(val, priv->mmio + (0x0e << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) val = readl(priv->mmio + (0x0f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) val &= ~GENMASK(7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val |= 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) writel(val, priv->mmio + (0x0f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case 25000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case 100000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (priv->mode == PHY_TYPE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* PLL KVCO tuning fine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) val = readl(priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) val &= ~(0x7 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) val |= 0x2 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) writel(val, priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Enable controlling random jitter, aka RMJ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) writel(0x4, priv->mmio + (0xb << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) val = readl(priv->mmio + (0x5 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) val &= ~(0x3 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) val |= 0x1 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writel(val, priv->mmio + (0x5 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) writel(0x32, priv->mmio + (0x11 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) writel(0xf0, priv->mmio + (0xa << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) } else if (priv->mode == PHY_TYPE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* downward spread spectrum +500ppm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) val = readl(priv->mmio + (0x1f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) val &= ~GENMASK(7, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) val |= 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) writel(val, priv->mmio + (0x1f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) val = readl(priv->mmio + (0xc << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) val |= 0x3 << 4 | 0x1 << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) writel(val, priv->mmio + (0xc << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) val = readl(priv->mmio + (0xd << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) val |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) writel(val, priv->mmio + (0xd << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) val = readl(priv->mmio + (0x7 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) val |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) writel(val, priv->mmio + (0x7 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* pipe-phy-grf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* pipe-grf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const struct clk_bulk_data rk3568_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { .id = "refclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { .id = "apbclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { .id = "pipe_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .num_clks = ARRAY_SIZE(rk3568_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .clks = rk3568_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .grfcfg = &rk3568_combphy_grfcfgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .combphy_cfg = rk3568_combphy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .force_det_out = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct clk *refclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Configure PHY reference clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) for (i = 0; i < priv->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (!strncmp(priv->clks[i].id, "refclk", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) refclk = priv->clks[i].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!refclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dev_err(priv->dev, "No refclk found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) switch (priv->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case PHY_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Set SSC downward spread spectrum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) val = readl(priv->mmio + (0x1f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) val &= ~GENMASK(5, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) val |= 0x01 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) writel(val, priv->mmio + 0x7c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) case PHY_TYPE_USB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* Set SSC downward spread spectrum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) val = readl(priv->mmio + (0x1f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) val &= ~GENMASK(5, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) val |= 0x01 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) writel(val, priv->mmio + 0x7c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Enable adaptive CTLE for USB3.0 Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) val = readl(priv->mmio + (0x0e << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) val &= ~GENMASK(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) val |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) writel(val, priv->mmio + (0x0e << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Set PLL KVCO fine tuning signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) val = readl(priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) val &= ~(0x7 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) val |= 0x2 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) writel(val, priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Set PLL LPF R1 to su_trim[10:7]=1001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) writel(0x4, priv->mmio + (0xb << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* Set PLL input clock divider 1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) val = readl(priv->mmio + (0x5 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) val &= ~(0x3 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) val |= 0x1 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) writel(val, priv->mmio + (0x5 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Set PLL loop divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) writel(0x32, priv->mmio + (0x11 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Set PLL KVCO to min and set PLL charge pump current to max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) writel(0xf0, priv->mmio + (0xa << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* Set Rx squelch input filler bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) writel(0x0d, priv->mmio + (0x14 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) param_write(priv->phy_grf, &cfg->usb_mode_set, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case PHY_TYPE_SATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Enable adaptive CTLE for SATA Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) val = readl(priv->mmio + (0x0e << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) val &= ~GENMASK(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) val |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) writel(val, priv->mmio + (0x0e << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) writel(0x8F, priv->mmio + (0x06 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) param_write(priv->phy_grf, &cfg->con0_for_sata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) param_write(priv->phy_grf, &cfg->con1_for_sata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) param_write(priv->phy_grf, &cfg->con2_for_sata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) param_write(priv->phy_grf, &cfg->con3_for_sata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case PHY_TYPE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case PHY_TYPE_QSGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_err(priv->dev, "incompatible PHY type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) rate = clk_get_rate(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) case 24000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) val = readl(priv->mmio + (0x0e << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) val &= ~GENMASK(7, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) val |= 0x01 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) writel(val, priv->mmio + (0x0e << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) val = readl(priv->mmio + (0x0f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) val &= ~GENMASK(7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) val |= 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) writel(val, priv->mmio + (0x0f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) } else if (priv->mode == PHY_TYPE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* PLL KVCO tuning fine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) val = readl(priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) val &= ~GENMASK(4, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) val |= 0x4 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) writel(val, priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Set up rx_trim */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) val = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) writel(val, priv->mmio + (0x1b << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Set up su_trim: T0_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) val = 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) writel(val, priv->mmio + (0xa << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) val = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) writel(val, priv->mmio + (0xb << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) val = 0x57;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) writel(val, priv->mmio + (0xd << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) val = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) writel(val, priv->mmio + (0xf << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case 25000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case 100000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (priv->mode == PHY_TYPE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* gate_tx_pck_sel length select work for L1SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) val = 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) writel(val, priv->mmio + 0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* PLL KVCO tuning fine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) val = readl(priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) val &= ~GENMASK(4, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) val |= 0x4 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) writel(val, priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) val = 0x4c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) writel(val, priv->mmio + (0x1b << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Set up su_trim: T3_P1 650mv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) val = 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) writel(val, priv->mmio + (0xa << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) val = 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) writel(val, priv->mmio + (0xb << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) val = 0x88;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) writel(val, priv->mmio + (0xc << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) val = 0x56;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) writel(val, priv->mmio + (0xd << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) } else if (priv->mode == PHY_TYPE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* downward spread spectrum +500ppm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) val = readl(priv->mmio + (0x1f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) val &= ~GENMASK(7, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) val |= 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) writel(val, priv->mmio + (0x1f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* ssc ppm adjust to 3500ppm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) val = readl(priv->mmio + (0x9 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) val &= ~GENMASK(3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) val |= 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) writel(val, priv->mmio + (0x9 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) val = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) writel(val, priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) val = 0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) writel(val, priv->mmio + (0x1b << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* Set up su_trim: T3_P1 650mv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) val = 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) writel(val, priv->mmio + (0xa << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) val = 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) writel(val, priv->mmio + (0xb << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) val = 0x88;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) writel(val, priv->mmio + (0xc << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) val = 0x56;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) writel(val, priv->mmio + (0xd << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) val = readl(priv->mmio + (0x7 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) val |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) writel(val, priv->mmio + (0x7 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (priv->mode == PHY_TYPE_PCIE && rate == 24000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Xin24M T0_1 650mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) writel(0x00, priv->mmio + (0x10 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) writel(0x32, priv->mmio + (0x11 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) writel(0x00, priv->mmio + (0x1b << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) writel(0x90, priv->mmio + (0x0a << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) writel(0x02, priv->mmio + (0x0b << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) writel(0x08, priv->mmio + (0x0c << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) writel(0x57, priv->mmio + (0x0d << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) writel(0x40, priv->mmio + (0x0e << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) writel(0x5f, priv->mmio + (0x0f << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) writel(0x10, priv->mmio + (0x20 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* pipe-phy-grf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* pipe-grf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .pipe_con1_for_sata = { 0x0004, 2, 0, 0x00, 0x2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static const struct clk_bulk_data rk3588_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) { .id = "refclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) { .id = "apbclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) { .id = "phpclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .num_clks = ARRAY_SIZE(rk3588_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .clks = rk3588_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .grfcfg = &rk3588_combphy_grfcfgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .combphy_cfg = rk3588_combphy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .force_det_out = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const struct of_device_id rockchip_combphy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .compatible = "rockchip,rk3568-naneng-combphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .data = &rk3568_combphy_cfgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .compatible = "rockchip,rk3588-naneng-combphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .data = &rk3588_combphy_cfgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static struct platform_driver rockchip_combphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .probe = rockchip_combphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .name = "naneng-combphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .of_match_table = rockchip_combphy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) module_platform_driver(rockchip_combphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags