^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Rockchip MIPI RX Synopsys/Innosilicon DPHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * COPYING in the main directory of this source tree, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * OpenIB.org BSD license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Redistribution and use in source and binary forms, with or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * without modification, are permitted provided that the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - Redistributions of source code must retain the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * - Redistributions in binary form must reproduce the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * disclaimer in the documentation and/or other materials
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/rockchip/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* GRF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RK1808_GRF_PD_VI_CON_OFFSET 0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RK3288_GRF_SOC_CON6 0x025c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RK3288_GRF_SOC_CON8 0x0264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RK3288_GRF_SOC_CON9 0x0268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RK3288_GRF_SOC_CON10 0x026c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RK3288_GRF_SOC_CON14 0x027c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RK3288_GRF_SOC_STATUS21 0x02d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RK3288_GRF_IO_VSEL 0x0380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RK3288_GRF_SOC_CON15 0x03a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RK3326_GRF_IO_VSEL_OFFSET 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RK3326_GRF_PD_VI_CON_OFFSET 0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RK3368_GRF_SOC_CON6_OFFSET 0x0418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RK3368_GRF_IO_VSEL_OFFSET 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RK3399_GRF_SOC_CON9 0x6224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RK3399_GRF_SOC_CON21 0x6254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RK3399_GRF_SOC_CON22 0x6258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RK3399_GRF_SOC_CON23 0x625c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RK3399_GRF_SOC_CON24 0x6260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RK3399_GRF_SOC_CON25 0x6264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RK3399_GRF_SOC_STATUS1 0xe2a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RK3399_GRF_IO_VSEL 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RV1126_GRF_CSIPHY0_CON 0x10200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RV1126_GRF_CSIPHY1_CON 0x10210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RV1126_GRF_IOFUNC_CON3 0x1026c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RV1126_GRF_PHY1_SEL_CIFLITE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RV1126_GRF_PHY1_SEL_ISP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RV1126_GRF_PHY1_SEL_CIF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RK3288_PHY_TEST_CTRL0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RK3288_PHY_TEST_CTRL1 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RK3288_PHY_SHUTDOWNZ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RK3288_PHY_RSTZ 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RK3399_PHY_TEST_CTRL0 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RK3399_PHY_TEST_CTRL1 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RK3399_PHY_SHUTDOWNZ 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RK3399_PHY_RSTZ 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLOCK_LANE_HS_RX_CONTROL 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LANE0_HS_RX_CONTROL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LANE1_HS_RX_CONTROL 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LANE2_HS_RX_CONTROL 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LANE3_HS_RX_CONTROL 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HS_RX_DATA_LANES_THS_SETTLE_CONTROL 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* LOW POWER MODE SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RK1808_CSI_DPHY_CTRL_LANE_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RK1808_CSI_DPHY_CTRL_PWRCTL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RK1808_CSI_DPHY_CTRL_DIG_RST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RK3326_CSI_DPHY_CTRL_LANE_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RK3326_CSI_DPHY_CTRL_PWRCTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RK3326_CSI_DPHY_CTRL_DIG_RST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RK3368_CSI_DPHY_CTRL_LANE_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RK3368_CSI_DPHY_CTRL_PWRCTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RK3368_CSI_DPHY_CTRL_DIG_RST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RV1126_CSI_DPHY_CTRL_LANE_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RV1126_CSI_DPHY_CTRL_PWRCTL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RV1126_CSI_DPHY_CTRL_DIG_RST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Configure the count time of the THS-SETTLE by protocol. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RK1808_CSI_DPHY_CLK_WR_THS_SETTLE 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) (RK1808_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) (RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) (RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RK3326_CSI_DPHY_CLK_WR_THS_SETTLE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (RK3326_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) (RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) (RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RK3326S_CSI_DPHY_CLK_WR_THS_SETTLE 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RK3326S_CSI_DPHY_LANE0_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (RK3326S_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RK3326S_CSI_DPHY_LANE1_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (RK3326S_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RK3326S_CSI_DPHY_LANE2_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (RK3326S_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RK3326S_CSI_DPHY_LANE3_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (RK3326S_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RK3326S_CSI_DPHY_CLK_MODE 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RK3368_CSI_DPHY_CLK_WR_THS_SETTLE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (RK3368_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) (RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) (RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) (RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RV1126_CSI_DPHY_CLK_WR_THS_SETTLE 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RV1126_CSI_DPHY_LANE0_WR_THS_SETTLE 0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RV1126_CSI_DPHY_LANE1_WR_THS_SETTLE 0x260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RV1126_CSI_DPHY_LANE2_WR_THS_SETTLE 0x2e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RV1126_CSI_DPHY_LANE3_WR_THS_SETTLE 0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Calibration reception enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RK1808_CSI_DPHY_CLK_CALIB_EN 0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RK1808_CSI_DPHY_LANE0_CALIB_EN 0x1e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RK1808_CSI_DPHY_LANE1_CALIB_EN 0x268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RK1808_CSI_DPHY_LANE2_CALIB_EN 0x2e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RK1808_CSI_DPHY_LANE3_CALIB_EN 0x368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RK3326_CSI_DPHY_CLK_CALIB_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RK3326_CSI_DPHY_LANE0_CALIB_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RK3326_CSI_DPHY_LANE1_CALIB_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RK3326_CSI_DPHY_LANE2_CALIB_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define RK3326_CSI_DPHY_LANE3_CALIB_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define RK3368_CSI_DPHY_CLK_CALIB_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RK3368_CSI_DPHY_LANE0_CALIB_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define RK3368_CSI_DPHY_LANE1_CALIB_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RK3368_CSI_DPHY_LANE2_CALIB_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RK3368_CSI_DPHY_LANE3_CALIB_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define RV1126_CSI_DPHY_CLK_CALIB_EN 0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define RV1126_CSI_DPHY_LANE0_CALIB_EN 0x1e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RV1126_CSI_DPHY_LANE1_CALIB_EN 0x268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define RV1126_CSI_DPHY_LANE2_CALIB_EN 0x2e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RV1126_CSI_DPHY_LANE3_CALIB_EN 0x368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RV1126_CSI_DPHY_MIPI_LVDS_MODEL 0x2cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define RV1126_CSI_DPHY_LVDS_MODE 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * CSI HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PHY_TESTEN_ADDR (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PHY_TESTEN_DATA (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PHY_TESTCLK (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PHY_TESTCLR (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define THS_SETTLE_COUNTER_THRESHOLD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define HIWORD_UPDATE(val, mask, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ((val) << (shift) | (mask) << ((shift) + 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) enum mipi_dphy_chip_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CHIP_ID_RK1808 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CHIP_ID_RK3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CHIP_ID_RK3326,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CHIP_ID_RK3368,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CHIP_ID_RK3399,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CHIP_ID_RK1126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CHIP_ID_RK3326S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enum mipi_dphy_rx_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MIPI_DPHY_RX_PAD_SINK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MIPI_DPHY_RX_PAD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MIPI_DPHY_RX_PADS_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) enum dphy_reg_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) GRF_DPHY_RX0_TURNDISABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) GRF_DPHY_RX0_FORCERXMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) GRF_DPHY_RX0_FORCETXSTOPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) GRF_DPHY_RX0_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) GRF_DPHY_RX0_TESTCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) GRF_DPHY_RX0_TESTCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) GRF_DPHY_RX0_TESTEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) GRF_DPHY_RX0_TESTDIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) GRF_DPHY_RX0_TURNREQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) GRF_DPHY_RX0_TESTDOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) GRF_DPHY_TX0_TURNDISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) GRF_DPHY_TX0_FORCERXMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) GRF_DPHY_TX0_FORCETXSTOPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) GRF_DPHY_TX0_TURNREQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) GRF_DPHY_TX1RX1_TURNDISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) GRF_DPHY_TX1RX1_FORCERXMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) GRF_DPHY_TX1RX1_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) GRF_DPHY_TX1RX1_MASTERSLAVEZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) GRF_DPHY_TX1RX1_BASEDIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) GRF_DPHY_TX1RX1_ENABLECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) GRF_DPHY_TX1RX1_TURNREQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) GRF_DPHY_RX1_SRC_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* rk3288 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) GRF_CON_DISABLE_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) GRF_CON_ISP_DPHY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) GRF_DSI_CSI_TESTBUS_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) GRF_DVP_V18SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* rk1808 & rk3326 & rv1126 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) GRF_DPHY_CSIPHY_FORCERXMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) GRF_DPHY_CSIPHY_CLKLANE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) GRF_DPHY_CSIPHY_DATALANE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* rv1126 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) GRF_DPHY_CLK_INV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) GRF_DPHY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* rk3368 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) GRF_ISP_MIPI_CSI_HOST_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* below is for rk3399 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) GRF_DPHY_RX0_CLK_INV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) GRF_DPHY_RX1_CLK_INV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) GRF_DPHY_TX1RX1_SRC_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) enum csiphy_reg_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CSIPHY_CTRL_LANE_ENABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) CSIPHY_CTRL_PWRCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) CSIPHY_CTRL_DIG_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) CSIPHY_CLK_THS_SETTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CSIPHY_LANE0_THS_SETTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) CSIPHY_LANE1_THS_SETTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) CSIPHY_LANE2_THS_SETTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) CSIPHY_LANE3_THS_SETTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) CSIPHY_CLK_CALIB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) CSIPHY_LANE0_CALIB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) CSIPHY_LANE1_CALIB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) CSIPHY_LANE2_CALIB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) CSIPHY_LANE3_CALIB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) //rv1126 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CSIPHY_MIPI_LVDS_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CSIPHY_LVDS_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) CSIPHY_CLK_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) enum mipi_dphy_ctl_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MIPI_DPHY_CTL_GRF_ONLY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MIPI_DPHY_CTL_CSI_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) enum mipi_dphy_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MIPI_DPHY_LANE_CLOCK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MIPI_DPHY_LANE_DATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MIPI_DPHY_LANE_DATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MIPI_DPHY_LANE_DATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MIPI_DPHY_LANE_DATA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) enum txrx_reg_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) TXRX_PHY_TEST_CTRL0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) TXRX_PHY_TEST_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) TXRX_PHY_SHUTDOWNZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) TXRX_PHY_RSTZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct dphy_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct txrx_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct csiphy_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define PHY_REG(_offset, _width, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TXRX_REG(_offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { .offset = _offset, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CSIPHY_REG(_offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { .offset = _offset, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct dphy_reg rk1808_grf_dphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct dphy_reg rk3288_grf_dphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [GRF_CON_DISABLE_ISP] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) [GRF_CON_ISP_DPHY_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) [GRF_DSI_CSI_TESTBUS_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3288_GRF_SOC_CON14, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [GRF_DVP_V18SEL] = PHY_REG(RK3288_GRF_IO_VSEL, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3288_GRF_SOC_STATUS21, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct dphy_reg rk3326_grf_dphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) [GRF_DVP_V18SEL] = PHY_REG(RK3326_GRF_IO_VSEL_OFFSET, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct dphy_reg rk3368_grf_dphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) [GRF_DVP_V18SEL] = PHY_REG(RK3368_GRF_IO_VSEL_OFFSET, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [GRF_ISP_MIPI_CSI_HOST_SEL] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [GRF_CON_DISABLE_ISP] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct dphy_reg rk3399_grf_dphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [GRF_DPHY_TX1RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [GRF_DVP_V18SEL] = PHY_REG(RK3399_GRF_IO_VSEL, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct dphy_reg rv1126_grf_dphy0_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) [GRF_DPHY_CLK_INV_SEL] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) [GRF_DPHY_SEL] = PHY_REG(RV1126_GRF_IOFUNC_CON3, 3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const struct dphy_reg rv1126_grf_dphy1_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) [GRF_DPHY_CLK_INV_SEL] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [GRF_DPHY_SEL] = PHY_REG(RV1126_GRF_IOFUNC_CON3, 3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct txrx_reg rk3288_txrx_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [TXRX_PHY_TEST_CTRL0] = TXRX_REG(RK3288_PHY_TEST_CTRL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [TXRX_PHY_TEST_CTRL1] = TXRX_REG(RK3288_PHY_TEST_CTRL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) [TXRX_PHY_SHUTDOWNZ] = TXRX_REG(RK3288_PHY_SHUTDOWNZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) [TXRX_PHY_RSTZ] = TXRX_REG(RK3288_PHY_RSTZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct txrx_reg rk3399_txrx_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) [TXRX_PHY_TEST_CTRL0] = TXRX_REG(RK3399_PHY_TEST_CTRL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) [TXRX_PHY_TEST_CTRL1] = TXRX_REG(RK3399_PHY_TEST_CTRL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) [TXRX_PHY_SHUTDOWNZ] = TXRX_REG(RK3399_PHY_SHUTDOWNZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) [TXRX_PHY_RSTZ] = TXRX_REG(RK3399_PHY_RSTZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct csiphy_reg rk1808_csiphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_LANE_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_PWRCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_DIG_RST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_CLK_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_CLK_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE0_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE1_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE2_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE3_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const struct csiphy_reg rk3326_csiphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_LANE_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_PWRCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_DIG_RST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct csiphy_reg rk3326s_csiphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_LANE_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_PWRCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_DIG_RST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_CLK_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE0_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE1_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE2_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE3_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) [CSIPHY_CLK_MODE] = CSIPHY_REG(RK3326S_CSI_DPHY_CLK_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const struct csiphy_reg rk3368_csiphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_LANE_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_PWRCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_DIG_RST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_CLK_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_CLK_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE0_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE1_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE2_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE3_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct csiphy_reg rv1126_csiphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_LANE_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_PWRCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_DIG_RST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_CLK_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE0_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE1_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE2_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE3_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_CLK_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE0_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE1_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE2_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE3_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) [CSIPHY_MIPI_LVDS_MODEL] = CSIPHY_REG(RV1126_CSI_DPHY_MIPI_LVDS_MODEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) [CSIPHY_LVDS_MODE] = CSIPHY_REG(RV1126_CSI_DPHY_LVDS_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct hsfreq_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 range_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u8 cfg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct mipidphy_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct dphy_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) const char * const *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) const struct hsfreq_range *hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int num_hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) const struct dphy_reg *grf_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) const struct txrx_reg *txrx_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) const struct csiphy_reg *csiphy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) enum mipi_dphy_ctl_type ctl_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) void (*individual_init)(struct mipidphy_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) enum mipi_dphy_chip_id chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct sensor_async_subdev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct v4l2_async_subdev asd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct v4l2_mbus_config mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define MAX_DPHY_CLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define MAX_DPHY_SENSORS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct mipidphy_sensor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct v4l2_mbus_config mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct v4l2_mbus_framefmt format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct mipidphy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct regmap *regmap_grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) const struct dphy_reg *grf_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) const struct txrx_reg *txrx_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) const struct csiphy_reg *csiphy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) void __iomem *csihost_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct clk *clks[MAX_DPHY_CLK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) const struct dphy_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u64 data_rate_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct v4l2_async_notifier notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct mutex mutex; /* lock for updating protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct media_pad pads[MIPI_DPHY_RX_PADS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct mipidphy_sensor sensors[MAX_DPHY_SENSORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int num_sensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int phy_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) bool is_streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) void __iomem *txrx_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int (*stream_on)(struct mipidphy_priv *priv, struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int (*stream_off)(struct mipidphy_priv *priv, struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static inline struct mipidphy_priv *to_dphy_priv(struct v4l2_subdev *subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return container_of(subdev, struct mipidphy_priv, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static inline void write_grf_reg(struct mipidphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int index, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) const struct dphy_reg *reg = &priv->grf_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (reg->offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) regmap_write(priv->regmap_grf, reg->offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static inline u32 read_grf_reg(struct mipidphy_priv *priv, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) const struct dphy_reg *reg = &priv->grf_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (reg->offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) regmap_read(priv->regmap_grf, reg->offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) val = (val >> reg->shift) & reg->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static inline void write_txrx_reg(struct mipidphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int index, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) const struct txrx_reg *reg = &priv->txrx_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (reg->offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) writel(value, priv->txrx_base_addr + reg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static void mipidphy0_wr_reg(struct mipidphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u8 test_code, u8 test_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * is latched internally as the current test code. Test data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * programmed internally by rising edge on TESTCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void mipidphy1_wr_reg(struct mipidphy_priv *priv, unsigned char addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * TESTEN =1,TESTDIN=addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * TESTCLK=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * TESTEN =0,TESTDIN=data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * TESTCLK=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) write_txrx_reg(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_ADDR | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) write_txrx_reg(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_DATA | data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static inline void write_csiphy_reg(struct mipidphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int index, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) const struct csiphy_reg *reg = &priv->csiphy_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) writel(value, priv->csihost_base_addr + reg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static inline void read_csiphy_reg(struct mipidphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int index, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) const struct csiphy_reg *reg = &priv->csiphy_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *value = readl(priv->csihost_base_addr + reg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static void csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) enum mipi_dphy_lane lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) switch (lane) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case MIPI_DPHY_LANE_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) offset = CSIPHY_CLK_THS_SETTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) case MIPI_DPHY_LANE_DATA0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) offset = CSIPHY_LANE0_THS_SETTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) case MIPI_DPHY_LANE_DATA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) offset = CSIPHY_LANE1_THS_SETTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) case MIPI_DPHY_LANE_DATA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) offset = CSIPHY_LANE2_THS_SETTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case MIPI_DPHY_LANE_DATA3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) offset = CSIPHY_LANE3_THS_SETTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) read_csiphy_reg(priv, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) val = (val & ~0x7f) | hsfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) write_csiphy_reg(priv, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct media_pad *local, *remote;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct media_entity *sensor_me;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) local = &sd->entity.pads[MIPI_DPHY_RX_PAD_SINK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) remote = media_entity_remote_pad(local);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!remote) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) v4l2_warn(sd, "No link between dphy and sensor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) sensor_me = media_entity_remote_pad(local)->entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return media_entity_to_v4l2_subdev(sensor_me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static struct mipidphy_sensor *sd_to_sensor(struct mipidphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) for (i = 0; i < priv->num_sensors; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (priv->sensors[i].sd == sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return &priv->sensors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static int mipidphy_get_sensor_data_rate(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct mipidphy_priv *priv = to_dphy_priv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct v4l2_querymenu qm = { .id = V4L2_CID_LINK_FREQ, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) link_freq = v4l2_ctrl_find(sensor_sd->ctrl_handler, V4L2_CID_LINK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!link_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) v4l2_warn(sd, "No pixel rate control in subdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) qm.index = v4l2_ctrl_g_ctrl(link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ret = v4l2_querymenu(sensor_sd->ctrl_handler, &qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) v4l2_err(sd, "Failed to get menu item\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (!qm.value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) v4l2_err(sd, "Invalid link_freq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) priv->data_rate_mbps = qm.value * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) do_div(priv->data_rate_mbps, 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) v4l2_info(sd, "data_rate_mbps %lld\n", priv->data_rate_mbps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int mipidphy_update_sensor_mbus(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct mipidphy_priv *priv = to_dphy_priv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct v4l2_mbus_config mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret = v4l2_subdev_call(sensor_sd, pad, get_mbus_config, 0, &mbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) sensor->mbus = mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) switch (mbus.flags & V4L2_MBUS_CSI2_LANES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) case V4L2_MBUS_CSI2_1_LANE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) sensor->lanes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case V4L2_MBUS_CSI2_2_LANE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) sensor->lanes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case V4L2_MBUS_CSI2_3_LANE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) sensor->lanes = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case V4L2_MBUS_CSI2_4_LANE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) sensor->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static void rk1126_mipidphy_dphy_sel(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct mipidphy_priv *priv = to_dphy_priv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) char *model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u8 oldval, newval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) model = sd->v4l2_dev->mdev->model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) oldval = read_grf_reg(priv, GRF_DPHY_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) newval = oldval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (!strncmp(model, "rkcif_lite_mipi_lvds", sizeof("rkcif_lite_mipi_lvds") - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (priv->phy_index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) newval &= ~RV1126_GRF_PHY1_SEL_CIFLITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) newval |= RV1126_GRF_PHY1_SEL_CIFLITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) } else if (!strncmp(model, "rkcif_mipi_lvds", sizeof("rkcif_mipi_lvds") - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (priv->phy_index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) newval &= ~RV1126_GRF_PHY1_SEL_CIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) newval |= RV1126_GRF_PHY1_SEL_CIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (priv->phy_index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) newval &= ~RV1126_GRF_PHY1_SEL_ISP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) newval |= RV1126_GRF_PHY1_SEL_ISP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (newval != oldval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) write_grf_reg(priv, GRF_DPHY_SEL, newval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int mipidphy_s_stream_start(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct mipidphy_priv *priv = to_dphy_priv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (priv->is_streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = mipidphy_get_sensor_data_rate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (priv->drv_data->chip_id == CHIP_ID_RK1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) rk1126_mipidphy_dphy_sel(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) mipidphy_update_sensor_mbus(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) priv->stream_on(priv, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) priv->is_streaming = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int mipidphy_s_stream_stop(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct mipidphy_priv *priv = to_dphy_priv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!priv->is_streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (priv->stream_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) priv->stream_off(priv, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) priv->is_streaming = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int mipidphy_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct mipidphy_priv *priv = to_dphy_priv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_info(priv->dev, "stream on:%d\n", on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mutex_lock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = mipidphy_s_stream_start(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret = mipidphy_s_stream_stop(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) mutex_unlock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static int mipidphy_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct v4l2_subdev *sensor = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return v4l2_subdev_call(sensor, video, g_frame_interval, fi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int mipidphy_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct mipidphy_priv *priv = to_dphy_priv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct mipidphy_sensor *sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (!sensor_sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) sensor = sd_to_sensor(priv, sensor_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) mipidphy_update_sensor_mbus(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) *config = sensor->mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int mipidphy_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct mipidphy_priv *priv = to_dphy_priv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return pm_runtime_get_sync(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return pm_runtime_put(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int mipidphy_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct media_entity *me = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct mipidphy_priv *priv = to_dphy_priv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int i, num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) num_clks = priv->drv_data->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) for (i = num_clks - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (!IS_ERR(priv->clks[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) clk_disable_unprepare(priv->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int mipidphy_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct media_entity *me = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct mipidphy_priv *priv = to_dphy_priv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) int i, num_clks, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) num_clks = priv->drv_data->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (!IS_ERR(priv->clks[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = clk_prepare_enable(priv->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) clk_disable_unprepare(priv->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* dphy accepts all fmt/size from sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int mipidphy_get_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct mipidphy_priv *priv = to_dphy_priv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * Do not allow format changes and just relay whatever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * set currently in the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (!sensor_sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ret = v4l2_subdev_call(sensor_sd, pad, get_fmt, NULL, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (!ret && fmt->pad == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) sensor->format = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static int mipidphy_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct v4l2_subdev *sensor = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return v4l2_subdev_call(sensor, pad, get_selection, NULL, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static const struct v4l2_subdev_pad_ops mipidphy_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .set_fmt = mipidphy_get_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .get_fmt = mipidphy_get_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .get_selection = mipidphy_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .get_mbus_config = mipidphy_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static const struct v4l2_subdev_core_ops mipidphy_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .s_power = mipidphy_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static const struct v4l2_subdev_video_ops mipidphy_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .g_frame_interval = mipidphy_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .s_stream = mipidphy_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static const struct v4l2_subdev_ops mipidphy_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .core = &mipidphy_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .video = &mipidphy_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .pad = &mipidphy_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* These tables must be sorted by .range_h ascending. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static const struct hsfreq_range rk1808_rv1126_mipidphy_hsfreq_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) { 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) { 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static const struct hsfreq_range rk3288_mipidphy_hsfreq_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) { 999, 0x1a}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const struct hsfreq_range rk3326_mipidphy_hsfreq_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) { 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) { 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) { 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static const struct hsfreq_range rk3326s_mipidphy_hsfreq_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) { 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) { 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static const struct hsfreq_range rk3368_mipidphy_hsfreq_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) { 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) { 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) { 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) { 999, 0x1a}, {1049, 0x2a}, {1099, 0x3a}, {1149, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {1199, 0x1b}, {1249, 0x2b}, {1299, 0x3b}, {1349, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {1399, 0x1c}, {1449, 0x2c}, {1500, 0x3c}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const char * const rk1808_mipidphy_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static const char * const rk3288_mipidphy_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) "dphy-ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static const char * const rk3326_mipidphy_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "dphy-ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static const char * const rk3368_mipidphy_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) "pclk_dphyrx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static const char * const rk3399_mipidphy_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "dphy-ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "dphy-cfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) "grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "pclk_mipi_dsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static const char * const rv1126_mipidphy_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static void default_mipidphy_individual_init(struct mipidphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static void rk3368_mipidphy_individual_init(struct mipidphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* isp select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) write_grf_reg(priv, GRF_ISP_MIPI_CSI_HOST_SEL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static void rk3399_mipidphy_individual_init(struct mipidphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * According to the sequence of RK3399_TXRX_DPHY, the setting of isp0 mipi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * will affect txrx dphy in default state of grf_soc_con24.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static void rv1126_mipidphy_individual_init(struct mipidphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct device_node *parent = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct device_node *remote = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u8 val, sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) priv->grf_regs = priv->phy_index ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) rv1126_grf_dphy1_regs : rv1126_grf_dphy0_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) val = read_grf_reg(priv, GRF_DPHY_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* get port1 remote endpoint info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) remote = of_graph_get_remote_node(parent, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (remote) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (strstr(remote->name, "isp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) sel = !priv->phy_index ? 0 : RV1126_GRF_PHY1_SEL_ISP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) sel = !priv->phy_index ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) RV1126_GRF_PHY1_SEL_CIF | RV1126_GRF_PHY1_SEL_CIFLITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) of_node_put(remote);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) write_grf_reg(priv, GRF_DPHY_SEL, val | sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static int mipidphy_rx_stream_on(struct mipidphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) const struct dphy_drv_data *drv_data = priv->drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) int i, hsfreq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) for (i = 0; i < num_hsfreq_ranges; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) hsfreq = hsfreq_ranges[i].cfg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (i == num_hsfreq_ranges) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) i = num_hsfreq_ranges - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) hsfreq = hsfreq_ranges[i].cfg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* RK3288 isp connected to phy0-rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* Belowed is the sequence of mipi configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* Step1: set RSTZ = 1'b0, phy0 controlled by isp0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /* Step2: set SHUTDOWNZ = 1'b0, controlled by isp0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* Step3: set TESTCLEAR = 1'b1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* Step4: apply REFCLK signal with the appropriate frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* Step5: apply CFG_CLK signal with the appropriate frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* Step6: set MASTERSLAVEZ = 1'b0 (for SLAVE), phy0 default is slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* Step7: set BASEDIR_N = 1’b1 (for SLAVE), phy0 default is slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * Step8: set all REQUEST inputs to zero, need to wait 15ns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * step8.1:set lan turndisab as 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * step8.2:set lan turnrequest as 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) write_grf_reg(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) write_grf_reg(priv, GRF_DPHY_RX0_FORCERXMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) write_grf_reg(priv, GRF_DPHY_RX0_TURNREQUEST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /* Step9: set TESTCLR to low, need to wait 15ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * Step10: configure Test Code 0x44 hsfreqrange according to values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * step10.1:set clock lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * step10.2:set hsfreqrange by lane0(test code 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) hsfreq <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) mipidphy0_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) mipidphy0_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) mipidphy0_wr_reg(priv, LANE1_HS_RX_CONTROL, hsfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) mipidphy0_wr_reg(priv, LANE2_HS_RX_CONTROL, hsfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) mipidphy0_wr_reg(priv, LANE3_HS_RX_CONTROL, hsfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* Step11: Configure analog references: of Test Code 0x22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* Step12: Set ENABLE_N=1'b1, need to wait 5ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* set lane num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) write_grf_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* Step13: Set SHUTDOWNZ=1'b1, controlled by isp need to wait 5ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* Step14: Set RSTZ=1'b1, controlled by isp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * Step15: Wait until STOPSTATEDATA_N & STOPSTATECLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * outputs are asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) const struct dphy_drv_data *drv_data = priv->drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) int i, hsfreq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) for (i = 0; i < num_hsfreq_ranges; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) hsfreq = hsfreq_ranges[i].cfg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (i == num_hsfreq_ranges) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) i = num_hsfreq_ranges - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) hsfreq = hsfreq_ranges[i].cfg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) *Config rk3288:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) *step1:rk3288 isp connected to phy1-rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) *step2:rk3288 phy1-rx test bus connected to csi host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) *step3:rk3288 phy1-rx source selected as: isp = 1'b1,csi-host = 1'b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) write_grf_reg(priv, GRF_DSI_CSI_TESTBUS_SEL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) write_grf_reg(priv, GRF_DPHY_RX1_SRC_SEL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * Config rk3399：
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * step1:rk3399 phy1-rx source selected as:1'b0=isp1,1'b1=isp0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* Belowed is the sequence of mipi configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /* Step1: set RSTZ = 1'b0, phy1-rx controlled by isp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* Step2: set SHUTDOWNZ = 1'b0, phy1-rx controlled by isp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* Step3: set TESTCLR= 1'b1,TESTCLK=1'b1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLR | PHY_TESTCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* Step4: apply REFCLK signal with the appropriate frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* Step5: apply CFG_CLK signal with the appropriate frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * Step6: set MASTERSLAVEZ = 1'b0 (for SLAVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * phy1 is set as slave,controlled by isp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * Step7: set BASEDIR_N = 1’b1 (for SLAVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * phy1 is set as slave,controlled by isp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* Step8: set all REQUEST inputs to zero, need to wait 15ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCERXMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCETXSTOPMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNREQUEST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNDISABLE, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* Step9: set TESTCLR=1'b0,TESTCLK=1'b1 need to wait 15ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * Step10: configure Test Code 0x44 hsfreqrange according to values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * step10.1:set clock lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * step10.2:set hsfreqrange by lane0(test code 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) hsfreq <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) mipidphy1_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) mipidphy1_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) mipidphy1_wr_reg(priv, LANE1_HS_RX_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) mipidphy1_wr_reg(priv, LANE2_HS_RX_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) mipidphy1_wr_reg(priv, LANE3_HS_RX_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* Step11: Configure analog references: of Test Code 0x22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * Step12: Set ENABLE_N=1'b1, need to wait 5ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * Set lane num:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * for 3288,controlled by isp,enable lanes actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * is set by grf_soc_con9[12:15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * for 3399,controlled by isp1,enable lanes actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * is set by isp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * if run 3399 here operates grf_soc_con23[0:3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) write_grf_reg(priv, GRF_DPHY_TX1RX1_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) GENMASK(sensor->lanes - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * Step13:Set SHUTDOWNZ=1'b1, phy1-rx controlled by isp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * need to wait 5ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /* Step14:Set RSTZ=1'b1, phy1-rx controlled by isp*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * Step15:Wait until STOPSTATEDATA_N & STOPSTATECLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * outputs are asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static int csi_mipidphy_stream_on(struct mipidphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) const struct dphy_drv_data *drv_data = priv->drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int i, hsfreq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) u32 clk_mode = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* phy start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* set data lane num and enable clock lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ((GENMASK(sensor->lanes - 1, 0) << MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) (0x1 << MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT) | 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /* Reset dphy analog part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* Reset dphy digital part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (drv_data->chip_id == CHIP_ID_RK3326S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (sensor->mbus.flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) clk_mode = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) else if (sensor->mbus.flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) clk_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) write_csiphy_reg(priv, CSIPHY_CLK_MODE, clk_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* Disable MIPI internal logical and switch to LVDS bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x3e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) /* Enable LVDS mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) write_csiphy_reg(priv, CSIPHY_MIPI_LVDS_MODEL, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) switch (sensor->format.code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) case MEDIA_BUS_FMT_Y12_1X12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) case MEDIA_BUS_FMT_SRGGB12_1X12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) case MEDIA_BUS_FMT_SBGGR12_1X12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) case MEDIA_BUS_FMT_SGBRG12_1X12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) case MEDIA_BUS_FMT_SGRBG12_1X12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) val = 0x1f; //12bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) case MEDIA_BUS_FMT_Y10_1X10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) case MEDIA_BUS_FMT_SBGGR10_1X10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) case MEDIA_BUS_FMT_SRGGB10_1X10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) case MEDIA_BUS_FMT_SGBRG10_1X10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) case MEDIA_BUS_FMT_SGRBG10_1X10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) val = 0xf; //10bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) val = 0x2f; //8bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* Enable LVDS internal logical and select bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) write_csiphy_reg(priv, CSIPHY_LVDS_MODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* not into receive mode/wait stopstate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) write_grf_reg(priv, GRF_DPHY_CSIPHY_FORCERXMODE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) /* enable calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (priv->data_rate_mbps > 1500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) write_csiphy_reg(priv, CSIPHY_CLK_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (sensor->lanes > 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) write_csiphy_reg(priv, CSIPHY_LANE0_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (sensor->lanes > 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) write_csiphy_reg(priv, CSIPHY_LANE1_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (sensor->lanes > 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) write_csiphy_reg(priv, CSIPHY_LANE2_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (sensor->lanes > 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) write_csiphy_reg(priv, CSIPHY_LANE3_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* set clock lane and data lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) for (i = 0; i < num_hsfreq_ranges; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) hsfreq = hsfreq_ranges[i].cfg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (i == num_hsfreq_ranges) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) i = num_hsfreq_ranges - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) hsfreq = hsfreq_ranges[i].cfg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (sensor->lanes > 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (sensor->lanes > 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (sensor->lanes > 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (sensor->lanes > 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) write_grf_reg(priv, GRF_DPHY_CLK_INV_SEL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) write_grf_reg(priv, GRF_DPHY_CSIPHY_DATALANE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) GENMASK(sensor->lanes - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static int csi_mipidphy_stream_off(struct mipidphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /* disable all lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /* disable pll and ldo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static const struct dphy_drv_data rk1808_mipidphy_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .clks = rk1808_mipidphy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .num_clks = ARRAY_SIZE(rk1808_mipidphy_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .hsfreq_ranges = rk1808_rv1126_mipidphy_hsfreq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .num_hsfreq_ranges = ARRAY_SIZE(rk1808_rv1126_mipidphy_hsfreq_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .grf_regs = rk1808_grf_dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .csiphy_regs = rk1808_csiphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .individual_init = default_mipidphy_individual_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .chip_id = CHIP_ID_RK1808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static const struct dphy_drv_data rk3288_mipidphy_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .clks = rk3288_mipidphy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .num_clks = ARRAY_SIZE(rk3288_mipidphy_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .hsfreq_ranges = rk3288_mipidphy_hsfreq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .num_hsfreq_ranges = ARRAY_SIZE(rk3288_mipidphy_hsfreq_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .grf_regs = rk3288_grf_dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .txrx_regs = rk3288_txrx_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .ctl_type = MIPI_DPHY_CTL_GRF_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .individual_init = default_mipidphy_individual_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .chip_id = CHIP_ID_RK3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .clks = rk3326_mipidphy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .num_clks = ARRAY_SIZE(rk3326_mipidphy_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .hsfreq_ranges = rk3326_mipidphy_hsfreq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .num_hsfreq_ranges = ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .grf_regs = rk3326_grf_dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .csiphy_regs = rk3326_csiphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .individual_init = default_mipidphy_individual_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .chip_id = CHIP_ID_RK3326,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static const struct dphy_drv_data rk3326s_mipidphy_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .clks = rk3326_mipidphy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .num_clks = ARRAY_SIZE(rk3326_mipidphy_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .hsfreq_ranges = rk3326s_mipidphy_hsfreq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .num_hsfreq_ranges = ARRAY_SIZE(rk3326s_mipidphy_hsfreq_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .grf_regs = rk3326_grf_dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .csiphy_regs = rk3326s_csiphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .individual_init = default_mipidphy_individual_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .chip_id = CHIP_ID_RK3326S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static const struct dphy_drv_data rk3368_mipidphy_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .clks = rk3368_mipidphy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .num_clks = ARRAY_SIZE(rk3368_mipidphy_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .hsfreq_ranges = rk3368_mipidphy_hsfreq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .num_hsfreq_ranges = ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .grf_regs = rk3368_grf_dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .csiphy_regs = rk3368_csiphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .individual_init = rk3368_mipidphy_individual_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .chip_id = CHIP_ID_RK3368,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static const struct dphy_drv_data rk3399_mipidphy_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .clks = rk3399_mipidphy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .grf_regs = rk3399_grf_dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .txrx_regs = rk3399_txrx_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .ctl_type = MIPI_DPHY_CTL_GRF_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .individual_init = rk3399_mipidphy_individual_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .chip_id = CHIP_ID_RK3399,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static const struct dphy_drv_data rv1126_mipidphy_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .clks = rv1126_mipidphy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .num_clks = ARRAY_SIZE(rv1126_mipidphy_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .hsfreq_ranges = rk1808_rv1126_mipidphy_hsfreq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .num_hsfreq_ranges = ARRAY_SIZE(rk1808_rv1126_mipidphy_hsfreq_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .csiphy_regs = rv1126_csiphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .individual_init = rv1126_mipidphy_individual_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .chip_id = CHIP_ID_RK1126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) static const struct of_device_id rockchip_mipidphy_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .compatible = "rockchip,rk1808-mipi-dphy-rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .data = &rk1808_mipidphy_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .compatible = "rockchip,rk3288-mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .data = &rk3288_mipidphy_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .compatible = "rockchip,rk3326-mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .data = &rk3326_mipidphy_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .compatible = "rockchip,rk3326s-mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .data = &rk3326s_mipidphy_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .compatible = "rockchip,rk3368-mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .data = &rk3368_mipidphy_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .compatible = "rockchip,rk3399-mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .data = &rk3399_mipidphy_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .compatible = "rockchip,rv1126-csi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .data = &rv1126_mipidphy_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) MODULE_DEVICE_TABLE(of, rockchip_mipidphy_match_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /* The .bound() notifier callback when a match is found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) rockchip_mipidphy_notifier_bound(struct v4l2_async_notifier *notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) struct v4l2_async_subdev *asd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct mipidphy_priv *priv = container_of(notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) struct mipidphy_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) struct sensor_async_subdev *s_asd = container_of(asd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct sensor_async_subdev, asd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) struct mipidphy_sensor *sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) unsigned int pad, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (priv->num_sensors == ARRAY_SIZE(priv->sensors))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) sensor = &priv->sensors[priv->num_sensors++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) sensor->lanes = s_asd->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) sensor->mbus = s_asd->mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) sensor->sd = sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) dev_info(priv->dev, "match %s:bus type %d\n", sd->name, s_asd->mbus.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) for (pad = 0; pad < sensor->sd->entity.num_pads; pad++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (sensor->sd->entity.pads[pad].flags & MEDIA_PAD_FL_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (pad == sensor->sd->entity.num_pads) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) "failed to find src pad for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) sensor->sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) ret = media_create_pad_link(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) &sensor->sd->entity, pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) &priv->sd.entity, MIPI_DPHY_RX_PAD_SINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) priv->num_sensors != 1 ? 0 : MEDIA_LNK_FL_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) "failed to create link for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) sensor->sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /* The .unbind callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) rockchip_mipidphy_notifier_unbind(struct v4l2_async_notifier *notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct v4l2_async_subdev *asd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct mipidphy_priv *priv = container_of(notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct mipidphy_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct mipidphy_sensor *sensor = sd_to_sensor(priv, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) sensor->sd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static const struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) v4l2_async_notifier_operations rockchip_mipidphy_async_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .bound = rockchip_mipidphy_notifier_bound,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .unbind = rockchip_mipidphy_notifier_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) static int rockchip_mipidphy_fwnode_parse(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) struct v4l2_fwnode_endpoint *vep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) struct v4l2_async_subdev *asd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct sensor_async_subdev *s_asd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) container_of(asd, struct sensor_async_subdev, asd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct v4l2_mbus_config *config = &s_asd->mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (vep->base.port != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) dev_err(dev, "The PHY has only port 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (vep->bus_type == V4L2_MBUS_CSI2_DPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) config->flags = vep->bus.mipi_csi2.flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) } else if (vep->bus_type == V4L2_MBUS_CCP2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) /* V4L2_MBUS_CCP2 for lvds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) config->type = V4L2_MBUS_CCP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) s_asd->lanes = vep->bus.mipi_csi1.data_lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) dev_err(dev, "Only CSI2 and CCP2 bus type is currently supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) switch (s_asd->lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) config->flags |= V4L2_MBUS_CSI2_1_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) config->flags |= V4L2_MBUS_CSI2_2_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) config->flags |= V4L2_MBUS_CSI2_3_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) config->flags |= V4L2_MBUS_CSI2_4_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static int rockchip_mipidphy_media_init(struct mipidphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) priv->pads[MIPI_DPHY_RX_PAD_SOURCE].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) priv->pads[MIPI_DPHY_RX_PAD_SINK].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) ret = media_entity_pads_init(&priv->sd.entity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) MIPI_DPHY_RX_PADS_NUM, priv->pads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) v4l2_async_notifier_init(&priv->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) priv->dev, &priv->notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) sizeof(struct sensor_async_subdev), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) rockchip_mipidphy_fwnode_parse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) priv->sd.subdev_notifier = &priv->notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) priv->notifier.ops = &rockchip_mipidphy_async_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) "failed to register async notifier : %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) v4l2_async_notifier_cleanup(&priv->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) return v4l2_async_register_subdev(&priv->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static int rockchip_mipidphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) struct mipidphy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) const struct dphy_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) of_id = of_match_device(rockchip_mipidphy_match_id, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) grf = syscon_node_to_regmap(dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) grf = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if (IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) dev_err(dev, "Can't find GRF syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) priv->regmap_grf = grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) priv->phy_index = of_alias_get_id(dev->of_node, "dphy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (priv->phy_index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) priv->phy_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) drv_data = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (soc_is_px30s())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) drv_data = &rk3326s_mipidphy_drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) for (i = 0; i < drv_data->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) priv->clks[i] = devm_clk_get(dev, drv_data->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (IS_ERR(priv->clks[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) dev_dbg(dev, "Failed to get %s\n", drv_data->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) priv->grf_regs = drv_data->grf_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) priv->txrx_regs = drv_data->txrx_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) priv->csiphy_regs = drv_data->csiphy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) priv->drv_data = drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (drv_data->ctl_type == MIPI_DPHY_CTL_CSI_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) priv->csihost_base_addr = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) priv->stream_on = csi_mipidphy_stream_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) priv->stream_off = csi_mipidphy_stream_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) priv->stream_on = mipidphy_txrx_stream_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) priv->txrx_base_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) priv->txrx_base_addr = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (IS_ERR(priv->txrx_base_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) priv->stream_on = mipidphy_rx_stream_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) priv->stream_off = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) sd = &priv->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) mutex_init(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) v4l2_subdev_init(sd, &mipidphy_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) snprintf(sd->name, sizeof(sd->name), "rockchip-mipi-dphy-rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) sd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) platform_set_drvdata(pdev, &sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ret = rockchip_mipidphy_media_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) goto destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) drv_data->individual_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) mutex_destroy(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) static int rockchip_mipidphy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) struct media_entity *me = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) struct mipidphy_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) mutex_destroy(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static const struct dev_pm_ops rockchip_mipidphy_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) SET_RUNTIME_PM_OPS(mipidphy_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) mipidphy_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static struct platform_driver rockchip_isp_mipidphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .probe = rockchip_mipidphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .remove = rockchip_mipidphy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .name = "rockchip-mipi-dphy-rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .pm = &rockchip_mipidphy_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .of_match_table = rockchip_mipidphy_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) module_platform_driver(rockchip_isp_mipidphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) MODULE_AUTHOR("Rockchip Camera/ISP team");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) MODULE_DESCRIPTION("Rockchip MIPI RX DPHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) MODULE_LICENSE("Dual BSD/GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags