^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Wyon Bi <bivvy.bi@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* 0x0030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DISABLE_PLL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* 0x003c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL_LOCK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* 0x0084 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ENABLE_TX BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct inno_video_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct reg_sequence ttl_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { 0x0000, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { 0x0004, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { 0x0008, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { 0x0010, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { 0x0014, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { 0x0080, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { 0x0100, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { 0x0104, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { 0x0108, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { 0x0110, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { 0x0114, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { 0x0180, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const struct reg_sequence lvds_mode_single_channel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { 0x0000, 0xbf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { 0x0004, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { 0x0008, 0xfe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 0x0010, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 0x0014, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { 0x0080, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { 0x0100, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { 0x0104, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 0x0108, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 0x0110, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { 0x0114, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { 0x0180, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct reg_sequence lvds_mode_dual_channel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 0x0000, 0xbf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 0x0004, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 0x0008, 0xfe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { 0x0010, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 0x0014, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { 0x0080, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 0x0100, 0xbf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 0x0104, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 0x0108, 0xfe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 0x0110, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 0x0114, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { 0x0180, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int inno_video_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct inno_video_phy *inno = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum phy_mode mode = phy_get_mode(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const struct reg_sequence *wseq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bool dual_channel = phy_get_bus_width(phy) == 2 ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clk_prepare_enable(inno->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pm_runtime_get_sync(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case PHY_MODE_LVDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (dual_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) wseq = lvds_mode_dual_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) nregs = ARRAY_SIZE(lvds_mode_dual_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) wseq = lvds_mode_single_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) nregs = ARRAY_SIZE(lvds_mode_single_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) wseq = ttl_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) nregs = ARRAY_SIZE(ttl_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) regmap_multi_reg_write(inno->regmap, wseq, nregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) regmap_update_bits(inno->regmap, 0x0030, DISABLE_PLL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = regmap_read_poll_timeout(inno->regmap, 0x003c, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) status & PLL_LOCK, 50, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_err(inno->dev, "PLL is not lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) regmap_update_bits(inno->regmap, 0x0084, ENABLE_TX, ENABLE_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int inno_video_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct inno_video_phy *inno = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) regmap_update_bits(inno->regmap, 0x0084, ENABLE_TX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) regmap_update_bits(inno->regmap, 0x0030, DISABLE_PLL, DISABLE_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pm_runtime_put(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clk_disable_unprepare(inno->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int inno_video_phy_set_mode(struct phy *phy, enum phy_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct phy_ops inno_video_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .set_mode = inno_video_phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .power_on = inno_video_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .power_off = inno_video_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct regmap_config inno_video_phy_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .max_register = 0x0180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int inno_video_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct inno_video_phy *inno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) inno->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) platform_set_drvdata(pdev, inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) inno->regmap = devm_regmap_init_mmio(dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) &inno_video_phy_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (IS_ERR(inno->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = PTR_ERR(inno->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_err(dev, "failed to init regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) inno->pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (IS_ERR(inno->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_err(dev, "failed to get pclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return PTR_ERR(inno->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) inno->rst = devm_reset_control_get(dev, "rst");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (IS_ERR(inno->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(dev, "failed to get reset control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return PTR_ERR(inno->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) phy = devm_phy_create(dev, NULL, &inno_video_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_err(dev, "failed to create PHY: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) phy_set_drvdata(phy, inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_err(dev, "failed to register phy provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int inno_video_phy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct of_device_id inno_video_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { .compatible = "rockchip,rk3288-video-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MODULE_DEVICE_TABLE(of, inno_video_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct platform_driver inno_video_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .name = "inno-video-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .of_match_table = of_match_ptr(inno_video_phy_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .probe = inno_video_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .remove = inno_video_phy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) module_platform_driver(inno_video_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_DESCRIPTION("Innosilicon LVDS/TTL PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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