^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Wyon Bi <bivvy.bi@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PSEC_PER_SEC 1000000000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * is the first address, the other from the bit4 to bit0 is the second address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * when you configure the registers, you must set both of them. The Clock Lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * and Data Lane use the same registers with the same second address, but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * first address is different.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FIRST_ADDRESS(x) (((x) & 0x7) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SECOND_ADDRESS(second))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Analog Register Part: reg00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BANDGAP_POWER_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BANDGAP_POWER_DOWN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BANDGAP_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LANE_EN_MASK GENMASK(6, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LANE_EN_CK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LANE_EN_3 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LANE_EN_2 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LANE_EN_1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LANE_EN_0 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define POWER_WORK_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Analog Register Part: reg01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_SYNCRST_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_SYNCRST_RESET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_SYNCRST_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_LDOPD_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_LDOPD_POWER_DOWN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_LDOPD_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_PLLPD_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_PLLPD_POWER_DOWN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_PLLPD_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Analog Register Part: reg03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_FBDIV_HI_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_PREDIV_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_PREDIV(x) UPDATE(x, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Analog Register Part: reg04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_FBDIV_LO_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Analog Register Part: reg05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Analog Register Part: reg06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Analog Register Part: reg07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Analog Register Part: reg08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SAMPLE_CLOCK_DIRECTION_FORWARD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define LOWFRE_EN_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Analog Register Part: reg1e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PLL_MODE_SEL_MASK GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PLL_MODE_SEL_LVDS_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PLL_MODE_SEL_MIPI_MODE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Digital Register Part: reg00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define REG_DIG_RSTN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define REG_DIG_RSTN_NORMAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define REG_DIG_RSTN_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Digital Register Part: reg01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define INVERT_TXCLKESC_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define INVERT_TXCLKESC_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define INVERT_TXCLKESC_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define INVERT_TXBYTECLKHS_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define INVERT_TXBYTECLKHS_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define INVERT_TXBYTECLKHS_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define T_LPX_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define T_LPX_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define T_HS_ZERO_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define T_HS_EXIT_CNT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define T_CLK_POST_CNT_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define T_CLK_POST_CNT(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LPDT_TX_PPI_SYNC_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LPDT_TX_PPI_SYNC_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LPDT_TX_PPI_SYNC_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define T_TA_GO_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define T_TA_SURE_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define T_TA_WAIT_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* LVDS Register Part: reg00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* LVDS Register Part: reg01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LVDS_DIGITAL_INTERNAL_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* LVDS Register Part: reg03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MODE_ENABLE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TTL_MODE_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define LVDS_MODE_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MIPI_MODE_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* LVDS Register Part: reg0b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LVDS_LANE_EN_MASK GENMASK(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LVDS_DATA_LANE0_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LVDS_DATA_LANE1_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define LVDS_DATA_LANE2_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LVDS_DATA_LANE3_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LVDS_CLK_LANE_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LVDS_PLL_POWER_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LVDS_PLL_POWER_OFF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LVDS_PLL_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LVDS_BANDGAP_POWER_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define LVDS_BANDGAP_POWER_DOWN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define LVDS_BANDGAP_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DSI_PHY_RSTZ 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PHY_ENABLECLK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DSI_PHY_STATUS 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PHY_LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct mipi_dphy_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int clkmiss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int clkpost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int clkpre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int clkprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int clksettle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int clktermen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int clktrail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int clkzero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int dtermen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int eot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int hsexit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int hsprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int hszero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int hssettle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int hsskip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int hstrail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int taget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int tago;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int tasure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int wakeup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct inno_video_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct clk *pclk_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct clk *pclk_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void __iomem *phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void __iomem *host_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u16 fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) REGISTER_PART_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) REGISTER_PART_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) REGISTER_PART_CLOCK_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) REGISTER_PART_DATA0_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) REGISTER_PART_DATA1_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) REGISTER_PART_DATA2_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) REGISTER_PART_DATA3_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) REGISTER_PART_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static inline struct inno_video_phy *hw_to_inno(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return container_of(hw, struct inno_video_phy, pll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void phy_update_bits(struct inno_video_phy *inno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 first, u8 second, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 reg = PHY_REG(first, second) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int tmp, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) orig = readl(inno->phy_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) tmp = orig & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tmp |= val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel(tmp, inno->phy_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void host_update_bits(struct inno_video_phy *inno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int tmp, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) orig = readl(inno->host_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) tmp = orig & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tmp |= val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writel(tmp, inno->host_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned long period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Global Operation Timing Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) timing->clkmiss = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) timing->clkpost = 70000 + 52 * period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) timing->clkpre = 8 * period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) timing->clkprepare = 65000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) timing->clksettle = 95000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) timing->clktermen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) timing->clktrail = 80000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) timing->clkzero = 260000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) timing->dtermen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) timing->eot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) timing->hsexit = 120000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) timing->hsprepare = 65000 + 4 * period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) timing->hszero = 145000 + 6 * period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) timing->hssettle = 85000 + 6 * period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) timing->hsskip = 40000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) timing->hstrail = max(8 * period, 60000 + 4 * period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) timing->init = 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) timing->lpx = 60000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) timing->taget = 5 * timing->lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) timing->tago = 4 * timing->lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) timing->tasure = 2 * timing->lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) timing->wakeup = 1000000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct mipi_dphy_timing gotp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 hs_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u8 clk_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 data_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u8 hs_trail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } timings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { 110000000, 0x20, 0x16, 0x02, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { 150000000, 0x06, 0x16, 0x03, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { 200000000, 0x18, 0x17, 0x04, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { 250000000, 0x05, 0x17, 0x05, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { 300000000, 0x51, 0x18, 0x06, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { 400000000, 0x64, 0x19, 0x07, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { 500000000, 0x20, 0x1b, 0x07, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { 600000000, 0x6a, 0x1d, 0x08, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { 700000000, 0x3e, 0x1e, 0x08, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { 800000000, 0x21, 0x1f, 0x09, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {1000000000, 0x09, 0x20, 0x09, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 t_txbyteclkhs, t_txclkesc, ui;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 txbyteclkhs, txclkesc, esc_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Select MIPI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Configure PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Enable PLL and LDO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) REG_LDOPD_MASK | REG_PLLPD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Reset analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) REG_SYNCRST_MASK, REG_SYNCRST_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Reset digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) txbyteclkhs = inno->pll.rate / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) txclkesc = txbyteclkhs / esc_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ui = div_u64(PSEC_PER_SEC, inno->pll.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) memset(&gotp, 0, sizeof(gotp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mipi_dphy_timing_get_default(&gotp, ui);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * The value of counter for HS Ths-exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Ths-exit = Tpin_txbyteclkhs * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) hs_exit = DIV_ROUND_UP(gotp.hsexit, t_txbyteclkhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * The value of counter for HS Tclk-post
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Tclk-post = Tpin_txbyteclkhs * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) clk_post = DIV_ROUND_UP(gotp.clkpost, t_txbyteclkhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * The value of counter for HS Tclk-pre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Tclk-pre = Tpin_txbyteclkhs * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) clk_pre = DIV_ROUND_UP(gotp.clkpre, t_txbyteclkhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * The value of counter for HS Tlpx Time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * Tlpx = Tpin_txbyteclkhs * (2 + value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (lpx >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) lpx -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * The value of counter for HS Tta-go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Tta-go for turnaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Tta-go = Ttxclkesc * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ta_go = DIV_ROUND_UP(gotp.tago, t_txclkesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * The value of counter for HS Tta-sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Tta-sure for turnaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Tta-sure = Ttxclkesc * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ta_sure = DIV_ROUND_UP(gotp.tasure, t_txclkesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * The value of counter for HS Tta-wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * Tta-wait for turnaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Tta-wait = Ttxclkesc * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ta_wait = DIV_ROUND_UP(gotp.taget, t_txclkesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) for (i = 0; i < ARRAY_SIZE(timings); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (inno->pll.rate <= timings[i].rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (i == ARRAY_SIZE(timings))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) --i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) hs_prepare = timings[i].hs_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) hs_trail = timings[i].hs_trail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) clk_lane_hs_zero = timings[i].clk_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) data_lane_hs_zero = timings[i].data_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) wakeup = 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (i == REGISTER_PART_CLOCK_LANE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) hs_zero = clk_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) hs_zero = data_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) T_LPX_CNT(lpx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) T_HS_PREPARE_CNT(hs_prepare));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) T_HS_ZERO_CNT(hs_zero));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) T_HS_TRAIL_CNT(hs_trail));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) T_HS_EXIT_CNT(hs_exit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) T_CLK_POST_CNT(clk_post));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) T_CLK_PRE_CNT(clk_pre));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) T_WAKEUP_CNT_HI(wakeup >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) T_WAKEUP_CNT_LO(wakeup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) T_TA_GO_CNT(ta_go));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) T_TA_SURE_CNT(ta_sure));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) T_TA_WAIT_CNT(ta_wait));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Enable all lanes on analog part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) LANE_EN_1 | LANE_EN_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 prediv = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u16 fbdiv = 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Sample clock reverse direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) SAMPLE_CLOCK_DIRECTION_REVERSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PLL_OUTPUT_FREQUENCY_DIV_BY_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Select LVDS mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Configure PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) REG_PREDIV_MASK, REG_PREDIV(prediv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Enable PLL and Bandgap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = readl_relaxed_poll_timeout(inno->host_base + DSI_PHY_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) val, val & PHY_LOCK, 50, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_err(inno->dev, "PLL is not lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Select PLL mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Reset LVDS digital logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) LVDS_DIGITAL_INTERNAL_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) LVDS_DIGITAL_INTERNAL_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Enable LVDS digital logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) LVDS_DIGITAL_INTERNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Enable LVDS analog driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Select TTL mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MODE_ENABLE_MASK, TTL_MODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Reset digital logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) LVDS_DIGITAL_INTERNAL_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) LVDS_DIGITAL_INTERNAL_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Enable digital logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) LVDS_DIGITAL_INTERNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Enable analog driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Enable for clk lane in TTL mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int inno_video_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct inno_video_phy *inno = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) enum phy_mode mode = phy_get_mode(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) clk_prepare_enable(inno->pclk_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) clk_prepare_enable(inno->pclk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pm_runtime_get_sync(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Bandgap power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Enable power work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) POWER_WORK_MASK, POWER_WORK_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case PHY_MODE_MIPI_DPHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) inno_video_phy_mipi_mode_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) case PHY_MODE_LVDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) inno_video_phy_lvds_mode_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) inno_video_phy_ttl_mode_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int inno_video_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct inno_video_phy *inno = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) REG_LDOPD_MASK | REG_PLLPD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) POWER_WORK_MASK, POWER_WORK_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) LVDS_DIGITAL_INTERNAL_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pm_runtime_put(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) clk_disable_unprepare(inno->pclk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) clk_disable_unprepare(inno->pclk_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int inno_video_phy_set_mode(struct phy *phy, enum phy_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const struct phy_ops inno_video_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .set_mode = inno_video_phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .power_on = inno_video_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .power_off = inno_video_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static unsigned long inno_video_phy_pll_round_rate(struct inno_video_phy *inno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned long prate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u8 *prediv, u16 *fbdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned long best_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned long fref, fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u8 min_prediv, max_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u8 _prediv, best_prediv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u16 _fbdiv, best_fbdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 min_delta = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * The PLL output frequency can be calculated using a simple formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) fref = prate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (rate > 1000000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) fout = 1000000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) fout = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* 5Mhz < Fref / prediv < 40MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) min_prediv = DIV_ROUND_UP(fref, 40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) max_prediv = fref / 5000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) tmp = (u64)fout * _prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) do_div(tmp, fref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) _fbdiv = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * The all possible settings of feedback divider are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * 12, 13, 14, 16, ~ 511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (_fbdiv == 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (_fbdiv < 12 || _fbdiv > 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) tmp = (u64)_fbdiv * fref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) do_div(tmp, _prediv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) delta = abs(fout - tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!delta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) best_prediv = _prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) best_fbdiv = _fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) best_freq = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) } else if (delta < min_delta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) best_prediv = _prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) best_fbdiv = _fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) best_freq = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) min_delta = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (best_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) *prediv = best_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) *fbdiv = best_fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return best_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static long inno_video_phy_pll_clk_round_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct inno_video_phy *inno = hw_to_inno(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned long fin = *prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) unsigned long fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u16 fbdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u8 prediv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) fout = inno_video_phy_pll_round_rate(inno, fin, rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) &prediv, &fbdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_dbg(inno->dev, "fin=%lu, fout=%lu, prediv=%u, fbdiv=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *prate, fout, prediv, fbdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) inno->pll.prediv = prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) inno->pll.fbdiv = fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) inno->pll.rate = fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int inno_video_phy_pll_clk_set_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct inno_video_phy *inno = hw_to_inno(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) inno->pll.rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) inno_video_phy_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct inno_video_phy *inno = hw_to_inno(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return inno->pll.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static const struct clk_ops inno_video_phy_pll_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .round_rate = inno_video_phy_pll_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .set_rate = inno_video_phy_pll_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .recalc_rate = inno_video_phy_pll_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int inno_video_phy_pll_register(struct inno_video_phy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct device *dev = inno->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int phy_pll_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) char pll_name[20] = "video_phy_pll_";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) parent_name = __clk_get_name(inno->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) strcat(pll_name, phy_pll_num++ ? "1" : "0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) init.name = pll_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) init.ops = &inno_video_phy_pll_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) inno->pll.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) clk = devm_clk_register(dev, &inno->pll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_err(dev, "failed to register PLL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return of_clk_add_provider(dev->of_node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static void inno_video_phy_pll_unregister(struct inno_video_phy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct device *dev = inno->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) of_clk_del_provider(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int inno_video_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct inno_video_phy *inno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) inno->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) platform_set_drvdata(pdev, inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(dev, "invalid phy resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) inno->phy_base = devm_ioremap(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!inno->phy_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dev_err(dev, "invalid host resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) inno->host_base = devm_ioremap(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!inno->host_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) inno->ref_clk = devm_clk_get(dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (IS_ERR(inno->ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = PTR_ERR(inno->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_err(dev, "failed to get ref clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) inno->pclk_phy = devm_clk_get(dev, "pclk_phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (IS_ERR(inno->pclk_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = PTR_ERR(inno->pclk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_err(dev, "failed to get phy pclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) inno->pclk_host = devm_clk_get(dev, "pclk_host");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (IS_ERR(inno->pclk_host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = PTR_ERR(inno->pclk_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_err(dev, "failed to get host pclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) inno->rst = devm_reset_control_get(dev, "rst");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (IS_ERR(inno->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = PTR_ERR(inno->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_err(dev, "failed to get system reset control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) phy = devm_phy_create(dev, NULL, &inno_video_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dev_err(dev, "failed to create phy: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) phy_set_drvdata(phy, inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dev_err(dev, "failed to register phy provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ret = inno_video_phy_pll_register(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int inno_video_phy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct inno_video_phy *inno = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) pm_runtime_disable(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) inno_video_phy_pll_unregister(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static const struct of_device_id inno_video_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) { .compatible = "rockchip,px30-video-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) { .compatible = "rockchip,rk3128-video-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) { .compatible = "rockchip,rk3368-video-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) { .compatible = "rockchip,rk3568-video-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) MODULE_DEVICE_TABLE(of, inno_video_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static struct platform_driver inno_video_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .name = "inno-video-combo-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .of_match_table = of_match_ptr(inno_video_phy_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .probe = inno_video_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .remove = inno_video_phy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) module_platform_driver(inno_video_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) MODULE_DESCRIPTION("Innosilicon MIPI/LVDS/TTL Video Combo PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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