^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * is the first address, the other from the bit4 to bit0 is the second address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * when you configure the registers, you must set both of them. The Clock Lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * and Data Lane use the same registers with the same second address, but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * first address is different.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FIRST_ADDRESS(x) (((x) & 0x7) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define INNO_PHY_REG(first, second) (FIRST_ADDRESS(first) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SECOND_ADDRESS(second))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Analog Register Part: reg00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BANDGAP_POWER_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BANDGAP_POWER_DOWN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BANDGAP_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LANE_EN_MASK GENMASK(6, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LANE_EN_CK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LANE_EN_3 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LANE_EN_2 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LANE_EN_1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LANE_EN_0 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define POWER_WORK_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Analog Register Part: reg01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_SYNCRST_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_SYNCRST_RESET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_SYNCRST_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_LDOPD_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_LDOPD_POWER_DOWN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_LDOPD_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_PLLPD_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_PLLPD_POWER_DOWN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_PLLPD_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Analog Register Part: reg03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_FBDIV_HI_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_PREDIV_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define REG_PREDIV(x) UPDATE(x, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Analog Register Part: reg04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_FBDIV_LO_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Analog Register Part: reg05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_LANE_SKEW_PHASE_SET_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_LANE_SKEW_PHASE_SET(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Analog Register Part: reg06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LDO_OUTPUT_SET_HI_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LDO_OUTPUT_SET_HI(x) UPDATE(x, 7, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LANE_3_SKEW_PHASE_SET_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LANE_3_SKEW_PHASE_SET(x) UPDATE(x, 6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LDO_OUTPUT_SET_LO_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LDO_OUTPUT_SET_LO(x) UPDATE(x, 3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LANE_2_SKEW_PHASE_SET_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LANE_2_SKEW_PHASE_SET(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Analog Register Part: reg07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PRE_EMPHASIS_RANGE_SET_HI_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PRE_EMPHASIS_RANGE_SET_HI(x) UPDATE(x, 7, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LANE_1_SKEW_PHASE_SET_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LANE_1_SKEW_PHASE_SET(x) UPDATE(x, 6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PRE_EMPHASIS_RANGE_SET_LO_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PRE_EMPHASIS_RANGE_SET_LO(x) UPDATE(x, 3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define LANE_0_SKEW_PHASE_SET_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LANE_0_SKEW_PHASE_SET(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Analog Register Part: reg08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PRE_EMPHASIS_ENABLE_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PRE_EMPHASIS_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PRE_EMPHASIS_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PLL_POST_DIV_ENABLE_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PLL_POST_DIV_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PLL_POST_DIV_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DATA_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Analog Register Part: reg0b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VOD_MIN_RANGE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VOD_MID_RANGE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VOD_BIG_RANGE 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VOD_MAX_RANGE 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Analog Register Part: reg11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DATA_SAMPLE_PHASE_SET_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DATA_SAMPLE_PHASE_SET(x) UPDATE(x, 7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Digital Register Part: reg00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define REG_DIG_RSTN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define REG_DIG_RSTN_NORMAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define REG_DIG_RSTN_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Digital Register Part: reg01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define INV_PIN_TXCLKESC_0_ENABLE_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define INV_PIN_TXCLKESC_0_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define INV_PIN_TXCLKESC_0_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define INV_PIN_TXBYTECLKHS_ENABLE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define INV_PIN_TXBYTECLKHS_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define INV_PIN_TXBYTECLKHS_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DIFF_SIGNAL_SWAP_ENABLE_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DIFF_SIGNAL_SWAP_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DIFF_SIGNAL_SWAP_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define T_LPX_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define T_LPX_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define T_HS_ZERO_CNT_HI_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LPDT_TX_PPI_SYNC_ENABLE_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LPDT_TX_PPI_SYNC_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LPDT_TX_PPI_SYNC_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define T_CLK_POST_HI_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define T_CLK_POST_HI(x) UPDATE(x, 7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define T_TA_GO_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define T_HS_EXIT_CNT_HI_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define T_TA_SURE_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define T_TA_WAIT_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PSEC_PER_NSEC 1000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PSECS_PER_SEC 1000000000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) enum inno_video_phy_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) INNO_PHY_PADCTL_FUNC_MIPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) INNO_PHY_PADCTL_FUNC_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) INNO_PHY_PADCTL_FUNC_TTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) INNO_PHY_PADCTL_FUNC_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct mipi_dphy_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int clkmiss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int clkpost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int clkpre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int clkprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int clksettle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int clktermen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int clktrail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int clkzero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int dtermen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int eot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int hsexit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int hsprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int hszero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int hssettle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int hsskip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int hstrail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int taget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int tago;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int tasure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int wakeup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct inno_mipi_dphy_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int max_lane_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 hs_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 clk_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 data_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 hs_trail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct inno_mipi_dphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long lane_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u8 prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u16 fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) REGISTER_PART_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) REGISTER_PART_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) REGISTER_PART_CLOCK_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) REGISTER_PART_DATA0_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) REGISTER_PART_DATA1_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) REGISTER_PART_DATA2_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) REGISTER_PART_DATA3_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {1000, 0x05, 0x08, 0x20, 0x09, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {2200, 0x13, 0x64, 0x7e, 0x15, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {2400, 0x13, 0x33, 0x7f, 0x15, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {2500, 0x15, 0x54, 0x7f, 0x15, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline struct inno_mipi_dphy *hw_to_inno(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return container_of(hw, struct inno_mipi_dphy, pll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void inno_update_bits(struct inno_mipi_dphy *inno, u8 first, u8 second,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 reg = INNO_PHY_REG(first, second) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) regmap_update_bits(inno->regmap, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void inno_mipi_dphy_reset(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Reset analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) REG_SYNCRST_MASK, REG_SYNCRST_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Reset digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) inno_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) inno_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void inno_mipi_dphy_power_work_enable(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) POWER_WORK_MASK, POWER_WORK_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void inno_mipi_dphy_power_work_disable(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) POWER_WORK_MASK, POWER_WORK_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void inno_mipi_dphy_bandgap_power_enable(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void inno_mipi_dphy_bandgap_power_disable(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void inno_mipi_dphy_lane_enable(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 val = LANE_EN_CK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) switch (inno->lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) val |= LANE_EN_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) val |= LANE_EN_1 | LANE_EN_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) val |= LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) val |= LANE_EN_3 | LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void inno_mipi_dphy_lane_disable(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void inno_mipi_dphy_pll_enable(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) CLOCK_LANE_VOD_RANGE_SET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) REG_LDOPD_MASK | REG_PLLPD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void inno_mipi_dphy_pll_disable(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) REG_LDOPD_MASK | REG_PLLPD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Global Operation Timing Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) timing->clkmiss = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * The D-PHY spec define the clk post min time is 60ns + 52UI and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * no define max time, so we set 200 + 52UI leave move margin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) timing->clkpost = 200 + 52 * period / PSEC_PER_NSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) timing->clkpre = 8 * period / PSEC_PER_NSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) timing->clkprepare = 65;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) timing->clksettle = 95;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) timing->clktermen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) timing->clktrail = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) timing->clkzero = 260;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) timing->dtermen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) timing->eot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) timing->hsexit = 120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) timing->hsprepare = 65 + 4 * period / PSEC_PER_NSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) timing->hszero = 145 + 6 * period / PSEC_PER_NSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) timing->hssettle = 85 + 6 * period / PSEC_PER_NSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) timing->hsskip = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) timing->hstrail = max(8 * period / PSEC_PER_NSEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 60 + 4 * period / PSEC_PER_NSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) timing->init = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) timing->lpx = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) timing->taget = 5 * timing->lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) timing->tago = 4 * timing->lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) timing->tasure = 2 * timing->lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) timing->wakeup = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const struct inno_mipi_dphy_timing *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) inno_mipi_dphy_get_timing(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) const struct inno_mipi_dphy_timing *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int num_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int lane_mbps = inno->lane_rate / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) timings = inno_mipi_dphy_timing_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) for (i = 0; i < num_timings; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (lane_mbps <= timings[i].max_lane_mbps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (i == num_timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) --i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return &timings[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void inno_mipi_dphy_timing_init(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct mipi_dphy_timing gotp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) const struct inno_mipi_dphy_timing *timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned long txbyteclk, txclkesc, ui, sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int esc_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 hs_prepare, hs_trail, hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) memset(&gotp, 0, sizeof(gotp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) txbyteclk = inno->lane_rate / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sys_clk = clk_get_rate(inno->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) esc_clk_div = DIV_ROUND_UP(txbyteclk, 20000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) txclkesc = txbyteclk / esc_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ui = DIV_ROUND_CLOSEST_ULL(PSECS_PER_SEC, inno->lane_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_dbg(inno->dev, "txbyteclk=%ld, ui=%ld, sys_clk=%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) txbyteclk, ui, sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mipi_dphy_timing_get_default(&gotp, ui);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) timing = inno_mipi_dphy_get_timing(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) hs_exit = DIV_ROUND_UP(gotp.hsexit * txbyteclk, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) clk_post = DIV_ROUND_UP(gotp.clkpost * txbyteclk, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) clk_pre = DIV_ROUND_UP(gotp.clkpre * txbyteclk, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) wakeup = DIV_ROUND_UP(gotp.wakeup * sys_clk, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (wakeup > 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) wakeup = 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ta_go = DIV_ROUND_UP(gotp.tago * txclkesc, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ta_sure = DIV_ROUND_UP(gotp.tasure * txclkesc, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ta_wait = DIV_ROUND_UP(gotp.taget * txclkesc, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) lpx = timing->lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) hs_prepare = timing->hs_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) hs_trail = timing->hs_trail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (i == REGISTER_PART_CLOCK_LANE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) hs_zero = timing->clk_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) hs_zero = timing->data_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_dbg(inno->dev, "lpx=%x\n", lpx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_dbg(inno->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "hs_trail=%x, hs_exit=%x, hs_prepare=%x, hs_zero=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) hs_trail, hs_exit, hs_prepare, hs_zero);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_dbg(inno->dev, "clk_pre=%x, clk_post=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) clk_pre, clk_post);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_dbg(inno->dev, "ta_go=%x, ta_sure=%x, ta_wait=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ta_go, ta_sure, ta_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) inno_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) T_LPX_CNT(lpx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) inno_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) T_HS_PREPARE_CNT(hs_prepare));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) inno_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) T_HS_ZERO_CNT_HI(hs_zero >> 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) inno_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) T_HS_ZERO_CNT_LO(hs_zero));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) inno_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) T_HS_TRAIL_CNT(hs_trail));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) inno_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) T_HS_EXIT_CNT_HI(hs_exit >> 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) inno_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) T_HS_EXIT_CNT_LO(hs_exit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) inno_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) T_CLK_POST_HI(clk_post >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) inno_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) T_CLK_POST_CNT_LO(clk_post));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) inno_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) T_CLK_PRE_CNT(clk_pre));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) inno_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) T_WAKEUP_CNT_HI(wakeup >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) inno_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) T_WAKEUP_CNT_LO(wakeup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) inno_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) T_TA_GO_CNT(ta_go));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) inno_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) T_TA_SURE_CNT(ta_sure));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) inno_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) T_TA_WAIT_CNT(ta_wait));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static unsigned long inno_mipi_dphy_pll_round_rate(struct inno_mipi_dphy *inno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned long prate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u8 *prediv, u16 *fbdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) const struct inno_mipi_dphy_timing *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned int num_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned long best_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned int fin, fout, max_fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 min_prediv, max_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 _prediv, best_prediv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u16 _fbdiv, best_fbdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 min_delta = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) timings = inno_mipi_dphy_timing_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * The PLL output frequency can be calculated using a simple formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) fin = prate / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) fout = 2 * (rate / USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) max_fout = 2 * timings[num_timings - 1].max_lane_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (fout > max_fout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) fout = max_fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* constraint: 5Mhz < Fref / prediv < 40MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) min_prediv = DIV_ROUND_UP(fin, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) max_prediv = fin / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 delta, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) _fbdiv = fout * _prediv / fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * The all possible settings of feedback divider are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * 12, 13, 14, 16, ~ 511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if ((_fbdiv == 15) || (_fbdiv < 12) || (_fbdiv > 511))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) tmp = _fbdiv * fin / _prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) delta = abs(fout - tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (delta < min_delta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) best_prediv = _prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) best_fbdiv = _fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) min_delta = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) best_freq = tmp * USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (best_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) *prediv = best_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) *fbdiv = best_fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return best_freq / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int inno_mipi_dphy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct inno_mipi_dphy *inno = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) clk_prepare_enable(inno->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pm_runtime_get_sync(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) inno_mipi_dphy_bandgap_power_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) inno_mipi_dphy_power_work_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) inno_mipi_dphy_pll_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) inno_mipi_dphy_lane_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) inno_mipi_dphy_reset(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) inno_mipi_dphy_timing_init(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int inno_mipi_dphy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct inno_mipi_dphy *inno = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) inno_mipi_dphy_lane_disable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) inno_mipi_dphy_pll_disable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) inno_mipi_dphy_power_work_disable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) inno_mipi_dphy_bandgap_power_disable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pm_runtime_put(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) clk_disable_unprepare(inno->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct phy_ops inno_mipi_dphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .power_on = inno_mipi_dphy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .power_off = inno_mipi_dphy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static long inno_mipi_dphy_pll_clk_round_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct inno_mipi_dphy *inno = hw_to_inno(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned long fin = *prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unsigned long fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u16 fbdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u8 prediv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) fout = inno_mipi_dphy_pll_round_rate(inno, fin, rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) &prediv, &fbdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_dbg(inno->dev, "%s: fin=%lu, req_rate=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) __func__, *prate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_dbg(inno->dev, "%s: fout=%lu, prediv=%u, fbdiv=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) __func__, fout, prediv, fbdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) inno->pll.prediv = prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) inno->pll.fbdiv = fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int inno_mipi_dphy_pll_clk_set_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct inno_mipi_dphy *inno = hw_to_inno(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_dbg(inno->dev, "%s: rate: %lu Hz\n", __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) inno->lane_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) inno_mipi_dphy_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct inno_mipi_dphy *inno = hw_to_inno(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_dbg(inno->dev, "%s: rate: %lu Hz\n", __func__, inno->lane_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return inno->lane_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const struct clk_ops inno_mipi_dphy_pll_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .round_rate = inno_mipi_dphy_pll_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .set_rate = inno_mipi_dphy_pll_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .recalc_rate = inno_mipi_dphy_pll_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int inno_mipi_dphy_pll_register(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct device *dev = inno->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) parent_name = __clk_get_name(inno->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = of_property_read_string(np, "clock-output-names", &init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_err(dev, "Missing clock-output-names property: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) init.ops = &inno_mipi_dphy_pll_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) init.parent_names = (const char * const *)&parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) inno->pll.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) clk = devm_clk_register(dev, &inno->pll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_err(dev, "failed to register PLL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return of_clk_add_provider(np, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void inno_mipi_dphy_pll_unregister(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) of_clk_del_provider(inno->dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int inno_mipi_dphy_parse_dt(struct inno_mipi_dphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct device *dev = inno->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (of_property_read_u32(dev->of_node, "inno,lanes", &inno->lanes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) inno->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const struct regmap_config inno_mipi_dphy_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .max_register = 0x3ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int inno_mipi_dphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct inno_mipi_dphy *inno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) inno->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) platform_set_drvdata(pdev, inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ret = inno_mipi_dphy_parse_dt(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev_err(dev, "failed to parse DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) inno->regmap = devm_regmap_init_mmio(dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) &inno_mipi_dphy_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (IS_ERR(inno->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = PTR_ERR(inno->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev_err(dev, "failed to init regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) inno->ref_clk = devm_clk_get(dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (IS_ERR(inno->ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_err(dev, "failed to get reference clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return PTR_ERR(inno->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) inno->pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (IS_ERR(inno->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_err(dev, "failed to get pclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return PTR_ERR(inno->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) inno->rst = devm_reset_control_get(dev, "apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (IS_ERR(inno->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev_err(dev, "failed to get system reset control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return PTR_ERR(inno->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) inno->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (IS_ERR(inno->grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_err(dev, "failed to get grf regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return PTR_ERR(inno->grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) phy = devm_phy_create(dev, NULL, &inno_mipi_dphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_err(dev, "failed to create MIPI D-PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) phy_set_drvdata(phy, inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dev_err(dev, "failed to register phy provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = inno_mipi_dphy_pll_register(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static int inno_mipi_dphy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct inno_mipi_dphy *inno = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) inno_mipi_dphy_pll_unregister(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) pm_runtime_disable(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const struct of_device_id inno_mipi_dphy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { .compatible = "rockchip,rk1808-mipi-dphy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { .compatible = "rockchip,rk3568-mipi-dphy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { .compatible = "rockchip,rv1126-mipi-dphy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) MODULE_DEVICE_TABLE(of, inno_mipi_dphy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static struct platform_driver inno_mipi_dphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .name = "inno-mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .of_match_table = of_match_ptr(inno_mipi_dphy_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .probe = inno_mipi_dphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .remove = inno_mipi_dphy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static int __init inno_mipi_dphy_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return platform_driver_register(&inno_mipi_dphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) fs_initcall(inno_mipi_dphy_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static void __exit inno_mipi_dphy_driver_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) platform_driver_unregister(&inno_mipi_dphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) module_exit(inno_mipi_dphy_driver_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) module_platform_driver(inno_mipi_dphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) MODULE_DESCRIPTION("Innosilicon MIPI D-PHY Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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