^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Wyon Bi <bivvy.bi@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/phy/phy-mipi-dphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PSEC_PER_SEC 1000000000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * is the first address, the other from the bit4 to bit0 is the second address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * when you configure the registers, you must set both of them. The Clock Lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * and Data Lane use the same registers with the same second address, but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * first address is different.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FIRST_ADDRESS(x) (((x) & 0x7) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SECOND_ADDRESS(second))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Analog Register Part: reg00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BANDGAP_POWER_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BANDGAP_POWER_DOWN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BANDGAP_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LANE_EN_MASK GENMASK(6, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LANE_EN_CK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LANE_EN_3 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LANE_EN_2 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LANE_EN_1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LANE_EN_0 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define POWER_WORK_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Analog Register Part: reg01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_SYNCRST_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_SYNCRST_RESET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_SYNCRST_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_LDOPD_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_LDOPD_POWER_DOWN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_LDOPD_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_PLLPD_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_PLLPD_POWER_DOWN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_PLLPD_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Analog Register Part: reg03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_FBDIV_HI_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_FBDIV_HI(x) UPDATE((x >> 8), 5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_PREDIV_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_PREDIV(x) UPDATE(x, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Analog Register Part: reg04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_FBDIV_LO_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Analog Register Part: reg05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Analog Register Part: reg06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Analog Register Part: reg07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Analog Register Part: reg08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PRE_EMPHASIS_ENABLE_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PRE_EMPHASIS_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PRE_EMPHASIS_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PLL_POST_DIV_ENABLE_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PLL_POST_DIV_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PLL_POST_DIV_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DATA_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SAMPLE_CLOCK_DIRECTION_FORWARD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LOWFRE_EN_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Analog Register Part: reg1e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PLL_MODE_SEL_MASK GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PLL_MODE_SEL_LVDS_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PLL_MODE_SEL_MIPI_MODE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Analog Register Part: reg0b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VOD_MIN_RANGE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VOD_MID_RANGE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VOD_BIG_RANGE 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VOD_MAX_RANGE 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Digital Register Part: reg00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define REG_DIG_RSTN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define REG_DIG_RSTN_NORMAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define REG_DIG_RSTN_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Digital Register Part: reg01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define INVERT_TXCLKESC_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define INVERT_TXCLKESC_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define INVERT_TXCLKESC_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define INVERT_TXBYTECLKHS_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define INVERT_TXBYTECLKHS_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define INVERT_TXBYTECLKHS_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define T_LPX_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define T_LPX_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define T_HS_ZERO_CNT_HI_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LPDT_TX_PPI_SYNC_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LPDT_TX_PPI_SYNC_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LPDT_TX_PPI_SYNC_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define T_CLK_POST_HI_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define T_CLK_POST_HI(x) UPDATE(x, 7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define T_TA_GO_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define T_HS_EXIT_CNT_HI_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define T_TA_SURE_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define T_TA_WAIT_CNT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* LVDS Register Part: reg00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* LVDS Register Part: reg01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define LVDS_DIGITAL_INTERNAL_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* LVDS Register Part: reg03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MODE_ENABLE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TTL_MODE_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LVDS_MODE_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MIPI_MODE_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* LVDS Register Part: reg0b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define LVDS_LANE_EN_MASK GENMASK(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define LVDS_DATA_LANE0_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define LVDS_DATA_LANE1_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define LVDS_DATA_LANE2_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define LVDS_DATA_LANE3_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define LVDS_CLK_LANE_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define LVDS_PLL_POWER_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define LVDS_PLL_POWER_OFF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define LVDS_PLL_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define LVDS_BANDGAP_POWER_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define LVDS_BANDGAP_POWER_DOWN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define LVDS_BANDGAP_POWER_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DSI_PHY_RSTZ 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PHY_ENABLECLK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DSI_PHY_STATUS 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PHY_LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) enum phy_max_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MAX_1GHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MAX_2_5GHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct inno_mipi_dphy_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int max_lane_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 hs_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 clk_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 data_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 hs_trail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct inno_dsidphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct clk *pclk_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct clk *pclk_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void __iomem *phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void __iomem *host_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct phy_configure_opts_mipi_dphy dphy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const struct inno_dsidphy_plat_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct clk *pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u16 fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct inno_dsidphy_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) const unsigned int num_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) enum phy_max_rate max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) REGISTER_PART_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) REGISTER_PART_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) REGISTER_PART_CLOCK_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) REGISTER_PART_DATA0_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) REGISTER_PART_DATA1_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) REGISTER_PART_DATA2_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) REGISTER_PART_DATA3_LANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) REGISTER_PART_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1GHz[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 110, 0x0, 0x20, 0x16, 0x02, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 150, 0x0, 0x06, 0x16, 0x03, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 200, 0x0, 0x18, 0x17, 0x04, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 250, 0x0, 0x05, 0x17, 0x05, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 300, 0x0, 0x51, 0x18, 0x06, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 400, 0x0, 0x64, 0x19, 0x07, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 500, 0x0, 0x20, 0x1b, 0x07, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 600, 0x0, 0x6a, 0x1d, 0x08, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { 700, 0x0, 0x3e, 0x1e, 0x08, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { 800, 0x0, 0x21, 0x1f, 0x09, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {1000, 0x0, 0x09, 0x20, 0x09, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5GHz[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {1000, 0x05, 0x08, 0x20, 0x09, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {2200, 0x13, 0x64, 0x7e, 0x15, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {2400, 0x13, 0x33, 0x7f, 0x15, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {2500, 0x15, 0x54, 0x7f, 0x15, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return container_of(hw, struct inno_dsidphy, pll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void phy_update_bits(struct inno_dsidphy *inno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u8 first, u8 second, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 reg = PHY_REG(first, second) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int tmp, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) orig = readl(inno->phy_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tmp = orig & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) tmp |= val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel(tmp, inno->phy_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void host_update_bits(struct inno_dsidphy *inno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int tmp, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) orig = readl(inno->host_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) tmp = orig & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) tmp |= val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) writel(tmp, inno->host_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned long prate = clk_get_rate(inno->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long best_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long fref, fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u8 min_prediv, max_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 _prediv, best_prediv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u16 _fbdiv, best_fbdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 min_delta = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * The PLL output frequency can be calculated using a simple formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) fref = prate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (rate > 1000000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) fout = 1000000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) fout = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* 5Mhz < Fref / prediv < 40MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) min_prediv = DIV_ROUND_UP(fref, 40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) max_prediv = fref / 5000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tmp = (u64)fout * _prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) do_div(tmp, fref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) _fbdiv = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * The possible settings of feedback divider are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * 12, 13, 14, 16, ~ 511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (_fbdiv == 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (_fbdiv < 12 || _fbdiv > 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) tmp = (u64)_fbdiv * fref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) do_div(tmp, _prediv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) delta = abs(fout - tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!delta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) best_prediv = _prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) best_fbdiv = _fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) best_freq = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) } else if (delta < min_delta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) best_prediv = _prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) best_fbdiv = _fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) best_freq = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) min_delta = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (best_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) inno->pll.prediv = best_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) inno->pll.fbdiv = best_fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) inno->pll.rate = best_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return best_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct inno_mipi_dphy_timing *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) inno_mipi_dphy_get_timing(struct inno_dsidphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) const struct inno_mipi_dphy_timing *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int num_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int lane_mbps = inno->pll.rate / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) timings = inno->pdata->inno_mipi_dphy_timing_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) num_timings = inno->pdata->num_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) for (i = 0; i < num_timings; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (lane_mbps <= timings[i].max_lane_mbps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (i == num_timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) --i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return &timings[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static void inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_dsidphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) CLOCK_LANE_VOD_RANGE_SET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) REG_LDOPD_MASK | REG_PLLPD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void inno_mipi_dphy_max_1GHz_pll_enable(struct inno_dsidphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Configure PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Enable PLL and LDO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) REG_LDOPD_MASK | REG_PLLPD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void inno_mipi_dphy_reset(struct inno_dsidphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Reset analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) REG_SYNCRST_MASK, REG_SYNCRST_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Reset digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void inno_mipi_dphy_timing_init(struct inno_dsidphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 t_txbyteclkhs, t_txclkesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u32 txbyteclkhs, txclkesc, esc_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) const struct inno_mipi_dphy_timing *timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) txbyteclkhs = inno->pll.rate / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) txclkesc = txbyteclkhs / esc_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * The value of counter for HS Ths-exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Ths-exit = Tpin_txbyteclkhs * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * The value of counter for HS Tclk-post
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Tclk-post = Tpin_txbyteclkhs * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * The value of counter for HS Tclk-pre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * Tclk-pre = Tpin_txbyteclkhs * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) clk_pre = DIV_ROUND_UP(cfg->clk_pre, t_txbyteclkhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * The value of counter for HS Tta-go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * Tta-go for turnaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * Tta-go = Ttxclkesc * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * The value of counter for HS Tta-sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Tta-sure for turnaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * Tta-sure = Ttxclkesc * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * The value of counter for HS Tta-wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Tta-wait for turnaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Tta-wait = Ttxclkesc * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) timing = inno_mipi_dphy_get_timing(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * The value of counter for HS Tlpx Time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * Tlpx = Tpin_txbyteclkhs * (2 + value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (inno->pdata->max_rate == MAX_1GHZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (lpx >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) lpx -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) lpx = timing->lpx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) hs_prepare = timing->hs_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) hs_trail = timing->hs_trail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) clk_lane_hs_zero = timing->clk_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) data_lane_hs_zero = timing->data_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) wakeup = 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (i == REGISTER_PART_CLOCK_LANE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hs_zero = clk_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) hs_zero = data_lane_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) T_LPX_CNT(lpx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) T_HS_PREPARE_CNT(hs_prepare));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (inno->pdata->max_rate == MAX_2_5GHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) T_HS_ZERO_CNT_HI(hs_zero >> 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) T_HS_ZERO_CNT_LO(hs_zero));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) T_HS_TRAIL_CNT(hs_trail));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (inno->pdata->max_rate == MAX_2_5GHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) T_HS_EXIT_CNT_HI(hs_exit >> 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) T_HS_EXIT_CNT_LO(hs_exit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (inno->pdata->max_rate == MAX_2_5GHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) T_CLK_POST_HI(clk_post >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) T_CLK_POST_CNT_LO(clk_post));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) T_CLK_PRE_CNT(clk_pre));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) T_WAKEUP_CNT_HI(wakeup >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) T_WAKEUP_CNT_LO(wakeup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) T_TA_GO_CNT(ta_go));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) T_TA_SURE_CNT(ta_sure));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) T_TA_WAIT_CNT(ta_wait));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static void inno_mipi_dphy_lane_enable(struct inno_dsidphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u8 val = LANE_EN_CK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) switch (inno->lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) val |= LANE_EN_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) val |= LANE_EN_1 | LANE_EN_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) val |= LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) val |= LANE_EN_3 | LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Select MIPI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (inno->pdata->max_rate == MAX_2_5GHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) inno_mipi_dphy_max_2_5GHz_pll_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) inno_mipi_dphy_max_1GHz_pll_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) inno_mipi_dphy_reset(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) inno_mipi_dphy_timing_init(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) inno_mipi_dphy_lane_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) inno_mipi_dphy_lane_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u8 prediv = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u16 fbdiv = 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Sample clock reverse direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) SAMPLE_CLOCK_DIRECTION_REVERSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PLL_OUTPUT_FREQUENCY_DIV_BY_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Select LVDS mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Configure PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) REG_PREDIV_MASK, REG_PREDIV(prediv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* Enable PLL and Bandgap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Select PLL mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Reset LVDS digital logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) LVDS_DIGITAL_INTERNAL_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) LVDS_DIGITAL_INTERNAL_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Enable LVDS digital logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) LVDS_DIGITAL_INTERNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Enable LVDS analog driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static void inno_dsidphy_phy_ttl_mode_enable(struct inno_dsidphy *inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Select TTL mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) MODE_ENABLE_MASK, TTL_MODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Reset digital logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) LVDS_DIGITAL_INTERNAL_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) LVDS_DIGITAL_INTERNAL_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Enable digital logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) LVDS_DIGITAL_INTERNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Enable analog driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Enable for clk lane in TTL mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int inno_dsidphy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct inno_dsidphy *inno = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) enum phy_mode mode = phy_get_mode(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) clk_prepare_enable(inno->pclk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) clk_prepare_enable(inno->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) pm_runtime_get_sync(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* Bandgap power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Enable power work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) POWER_WORK_MASK, POWER_WORK_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case PHY_MODE_MIPI_DPHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) inno_dsidphy_mipi_mode_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case PHY_MODE_LVDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) inno_dsidphy_lvds_mode_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) inno_dsidphy_phy_ttl_mode_enable(inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static int inno_dsidphy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct inno_dsidphy *inno = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) REG_LDOPD_MASK | REG_PLLPD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) POWER_WORK_MASK, POWER_WORK_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) LVDS_DIGITAL_INTERNAL_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pm_runtime_put(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) clk_disable_unprepare(inno->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) clk_disable_unprepare(inno->pclk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static int inno_dsidphy_configure(struct phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) union phy_configure_opts *opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct inno_dsidphy *inno = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) enum phy_mode mode = phy_get_mode(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (mode != PHY_MODE_MIPI_DPHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) cfg->hs_clk_rate = inno->pll.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) opts->mipi_dphy.hs_clk_rate = inno->pll.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int inno_dsidphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct inno_dsidphy *inno = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) clk_prepare_enable(inno->pclk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) clk_prepare_enable(inno->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) pm_runtime_get_sync(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int inno_dsidphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct inno_dsidphy *inno = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pm_runtime_put(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) clk_disable_unprepare(inno->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) clk_disable_unprepare(inno->pclk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const struct phy_ops inno_dsidphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .configure = inno_dsidphy_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .set_mode = inno_dsidphy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .power_on = inno_dsidphy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .power_off = inno_dsidphy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .init = inno_dsidphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .exit = inno_dsidphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int inno_dsidphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct inno_dsidphy *inno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (!inno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) inno->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) inno->pdata = of_device_get_match_data(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) platform_set_drvdata(pdev, inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) inno->phy_base = devm_platform_ioremap_resource_byname(pdev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (IS_ERR(inno->phy_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return PTR_ERR(inno->phy_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_err(dev, "invalid host resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) inno->host_base = devm_ioremap(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (IS_ERR(inno->host_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return PTR_ERR(inno->host_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) inno->ref_clk = devm_clk_get(dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (IS_ERR(inno->ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = PTR_ERR(inno->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dev_err(dev, "failed to get ref clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) inno->pclk_phy = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (IS_ERR(inno->pclk_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ret = PTR_ERR(inno->pclk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dev_err(dev, "failed to get phy pclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) inno->pclk_host = devm_clk_get(dev, "pclk_host");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (IS_ERR(inno->pclk_host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ret = PTR_ERR(inno->pclk_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dev_err(dev, "failed to get host pclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) inno->rst = devm_reset_control_get(dev, "apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (IS_ERR(inno->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = PTR_ERR(inno->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_err(dev, "failed to get system reset control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) phy = devm_phy_create(dev, NULL, &inno_dsidphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(dev, "failed to create phy: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (of_property_read_u32(dev->of_node, "inno,lanes", &inno->lanes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) inno->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) phy_set_drvdata(phy, inno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret = PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_err(dev, "failed to register phy provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static const struct inno_dsidphy_plat_data px30_plat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .max_rate = MAX_1GHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static const struct inno_dsidphy_plat_data rk3568_plat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .max_rate = MAX_2_5GHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int inno_dsidphy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct inno_dsidphy *inno = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) pm_runtime_disable(inno->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static const struct of_device_id inno_dsidphy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) { .compatible = "rockchip,px30-dsi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .data = &px30_plat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .compatible = "rockchip,rk3128-dsi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .data = &px30_plat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .compatible = "rockchip,rk3368-dsi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .data = &px30_plat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .compatible = "rockchip,rk3568-dsi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .data = &rk3568_plat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .compatible = "rockchip,rv1126-mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .data = &rk3568_plat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) MODULE_DEVICE_TABLE(of, inno_dsidphy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static struct platform_driver inno_dsidphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .name = "inno-dsidphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .of_match_table = of_match_ptr(inno_dsidphy_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .probe = inno_dsidphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .remove = inno_dsidphy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) module_platform_driver(inno_dsidphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) MODULE_DESCRIPTION("Innosilicon MIPI/LVDS/TTL Video Combo PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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