Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Rockchip emmc PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2016 ROCKCHIP, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * The higher 16-bit of this register is used for write protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define HIWORD_UPDATE(val, mask, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		((val) << (shift) | (mask) << ((shift) + 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* Register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define GRF_EMMCPHY_CON0		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define GRF_EMMCPHY_CON1		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define GRF_EMMCPHY_CON2		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define GRF_EMMCPHY_CON3		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define GRF_EMMCPHY_CON4		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define GRF_EMMCPHY_CON5		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define GRF_EMMCPHY_CON6		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define GRF_EMMCPHY_STATUS		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PHYCTRL_PDB_MASK		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PHYCTRL_PDB_SHIFT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PHYCTRL_PDB_PWR_ON		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PHYCTRL_PDB_PWR_OFF		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PHYCTRL_ENDLL_MASK		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PHYCTRL_ENDLL_SHIFT		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PHYCTRL_ENDLL_ENABLE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PHYCTRL_ENDLL_DISABLE		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PHYCTRL_CALDONE_MASK		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PHYCTRL_CALDONE_SHIFT		0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PHYCTRL_CALDONE_DONE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PHYCTRL_CALDONE_GOING		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PHYCTRL_DLLRDY_MASK		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PHYCTRL_DLLRDY_SHIFT		0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PHYCTRL_DLLRDY_DONE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PHYCTRL_DLLRDY_GOING		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PHYCTRL_FREQSEL_200M		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PHYCTRL_FREQSEL_50M		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PHYCTRL_FREQSEL_100M		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PHYCTRL_FREQSEL_150M		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PHYCTRL_FREQSEL_MASK		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PHYCTRL_FREQSEL_SHIFT		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PHYCTRL_DR_MASK			0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PHYCTRL_DR_SHIFT		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PHYCTRL_DR_50OHM		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PHYCTRL_DR_33OHM		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PHYCTRL_DR_66OHM		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PHYCTRL_DR_100OHM		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PHYCTRL_DR_40OHM		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define PHYCTRL_OTAPDLYENA		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PHYCTRL_OTAPDLYENA_MASK		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PHYCTRL_OTAPDLYENA_SHIFT	0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PHYCTRL_OTAPDLYSEL_MASK		0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PHYCTRL_OTAPDLYSEL_SHIFT	0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PHYCTRL_IS_CALDONE(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	((((x) >> PHYCTRL_CALDONE_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	  PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PHYCTRL_IS_DLLRDY(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	((((x) >> PHYCTRL_DLLRDY_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	  PHYCTRL_DLLRDY_MASK) == PHYCTRL_DLLRDY_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) struct rockchip_emmc_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned int	reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct regmap	*reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct clk	*emmcclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	unsigned int drive_impedance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static int rockchip_emmc_phy_power(struct phy *phy, bool on_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned int caldone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned int dllrdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	unsigned int freqsel = PHYCTRL_FREQSEL_200M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 * Keep phyctrl_pdb and phyctrl_endll low to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * initialization of CALIO state M/C DFFs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	regmap_write(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		     rk_phy->reg_offset + GRF_EMMCPHY_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		     HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				   PHYCTRL_PDB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				   PHYCTRL_PDB_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	regmap_write(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		     rk_phy->reg_offset + GRF_EMMCPHY_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		     HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				   PHYCTRL_ENDLL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				   PHYCTRL_ENDLL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* Already finish power_off above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (on_off == PHYCTRL_PDB_PWR_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	rate = clk_get_rate(rk_phy->emmcclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (rate != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		unsigned long ideal_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		unsigned long diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		case 1 ... 74999999:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			ideal_rate = 50000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			freqsel = PHYCTRL_FREQSEL_50M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		case 75000000 ... 124999999:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			ideal_rate = 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			freqsel = PHYCTRL_FREQSEL_100M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		case 125000000 ... 174999999:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			ideal_rate = 150000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			freqsel = PHYCTRL_FREQSEL_150M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			ideal_rate = 200000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		diff = (rate > ideal_rate) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			rate - ideal_rate : ideal_rate - rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		 * In order for tuning delays to be accurate we need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 * pretty spot on for the DLL range, so warn if we're too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		 * far off.  Also warn if we're above the 200 MHz max.  Don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		 * warn for really slow rates since we won't be tuning then.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if ((rate > 50000000 && diff > 15000000) || (rate > 200000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * According to the user manual, calpad calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * cycle takes more than 2us without the minimal recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 * value, so we may need a little margin here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	udelay(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	regmap_write(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		     rk_phy->reg_offset + GRF_EMMCPHY_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		     HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				   PHYCTRL_PDB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				   PHYCTRL_PDB_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 * According to the user manual, it asks driver to wait 5us for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * calpad busy trimming. However it is documented that this value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 * PVT(A.K.A process,voltage and temperature) relevant, so some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 * failure cases are found which indicates we should be more tolerant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 * to calpad busy trimming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ret = regmap_read_poll_timeout(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				       rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				       caldone, PHYCTRL_IS_CALDONE(caldone),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				       0, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		pr_err("%s: caldone failed, ret=%d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* Set the frequency of the DLL operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	regmap_write(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		     rk_phy->reg_offset + GRF_EMMCPHY_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		     HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				   PHYCTRL_FREQSEL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	/* Turn on the DLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	regmap_write(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		     rk_phy->reg_offset + GRF_EMMCPHY_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		     HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				   PHYCTRL_ENDLL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				   PHYCTRL_ENDLL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * We turned on the DLL even though the rate was 0 because we the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * clock might be turned on later.  ...but we can't wait for the DLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * to lock when the rate is 0 because it will never lock with no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 * Technically we should be checking the lock later when the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 * is turned on, but for now we won't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 * After enabling analog DLL circuits docs say that we need 10.2 us if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * our source clock is at 50 MHz and that lock time scales linearly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 * with clock speed.  If we are powering on the PHY and the card clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	 * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 * Hopefully we won't be running at 100 kHz, but we should still make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 * sure we wait long enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 * NOTE: There appear to be corner cases where the DLL seems to take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 * extra long to lock for reasons that aren't understood.  In some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 * extreme cases we've seen it take up to over 10ms (!).  We'll be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 * generous and give it 50ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	ret = regmap_read_poll_timeout(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				       rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 				       dllrdy, PHYCTRL_IS_DLLRDY(dllrdy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				       0, 50 * USEC_PER_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		pr_err("%s: dllrdy failed. ret=%d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int rockchip_emmc_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * We purposely get the clock here and not in probe to avoid the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * circular dependency problem.  We expect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * - PHY driver to probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * - SDHCI driver to start probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 * - SDHCI driver to register it's clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * - SDHCI driver to get the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * - SDHCI driver to init the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 * The clock is optional, using clk_get_optional() to get the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 * and do error processing if the return value != NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 * NOTE: we don't do anything special for EPROBE_DEFER here.  Given the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 * above expected use case, EPROBE_DEFER isn't sensible to expect, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 * it's just like any other error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	rk_phy->emmcclk = clk_get_optional(&phy->dev, "emmcclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (IS_ERR(rk_phy->emmcclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		ret = PTR_ERR(rk_phy->emmcclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		dev_err(&phy->dev, "Error getting emmcclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		rk_phy->emmcclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int rockchip_emmc_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	clk_put(rk_phy->emmcclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int rockchip_emmc_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/* Power down emmc phy analog blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int rockchip_emmc_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* Drive impedance: from DTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	regmap_write(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		     rk_phy->reg_offset + GRF_EMMCPHY_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		     HIWORD_UPDATE(rk_phy->drive_impedance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				   PHYCTRL_DR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 				   PHYCTRL_DR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/* Output tap delay: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	regmap_write(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		     rk_phy->reg_offset + GRF_EMMCPHY_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		     HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 				   PHYCTRL_OTAPDLYENA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 				   PHYCTRL_OTAPDLYENA_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* Output tap delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	regmap_write(rk_phy->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		     rk_phy->reg_offset + GRF_EMMCPHY_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		     HIWORD_UPDATE(4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				   PHYCTRL_OTAPDLYSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 				   PHYCTRL_OTAPDLYSEL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* Power up emmc phy analog blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct phy_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.init		= rockchip_emmc_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.exit		= rockchip_emmc_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.power_on	= rockchip_emmc_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.power_off	= rockchip_emmc_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static u32 convert_drive_impedance_ohm(struct platform_device *pdev, u32 dr_ohm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	switch (dr_ohm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	case 100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		return PHYCTRL_DR_100OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	case 66:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return PHYCTRL_DR_66OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return PHYCTRL_DR_50OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	case 40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		return PHYCTRL_DR_40OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	case 33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		return PHYCTRL_DR_33OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	dev_warn(&pdev->dev, "Invalid value %u for drive-impedance-ohm.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		 dr_ohm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return PHYCTRL_DR_50OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int rockchip_emmc_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	struct rockchip_emmc_phy *rk_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	unsigned int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (!dev->parent || !dev->parent->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	grf = syscon_node_to_regmap(dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		dev_err(dev, "Missing rockchip,grf property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		return PTR_ERR(grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (!rk_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (of_property_read_u32(dev->of_node, "reg", &reg_offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		dev_err(dev, "missing reg property in node %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	rk_phy->reg_offset = reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	rk_phy->reg_base = grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	rk_phy->drive_impedance = PHYCTRL_DR_50OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (!of_property_read_u32(dev->of_node, "drive-impedance-ohm", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		rk_phy->drive_impedance = convert_drive_impedance_ohm(pdev, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	generic_phy = devm_phy_create(dev, dev->of_node, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (IS_ERR(generic_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		return PTR_ERR(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	phy_set_drvdata(generic_phy, rk_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	{ .compatible = "rockchip,rk3399-emmc-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct platform_driver rockchip_emmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	.probe		= rockchip_emmc_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		.name	= "rockchip-emmc-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		.of_match_table = rockchip_emmc_phy_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) module_platform_driver(rockchip_emmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_LICENSE("GPL v2");