^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip DP PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Yakir Yang <ykk@@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GRF_SOC_CON12 0x0274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GRF_EDP_PHY_SIDDQ_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct rockchip_dp_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk *phy_24m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int rockchip_set_phy_state(struct phy *phy, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ret = regmap_write(dp->grf, GRF_SOC_CON12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) GRF_EDP_PHY_SIDDQ_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ret = clk_prepare_enable(dp->phy_24m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) clk_disable_unprepare(dp->phy_24m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = regmap_write(dp->grf, GRF_SOC_CON12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GRF_EDP_PHY_SIDDQ_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int rockchip_dp_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return rockchip_set_phy_state(phy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int rockchip_dp_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return rockchip_set_phy_state(phy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct phy_ops rockchip_dp_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .power_on = rockchip_dp_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .power_off = rockchip_dp_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int rockchip_dp_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct rockchip_dp_phy *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!dev->parent || !dev->parent->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dp->phy_24m = devm_clk_get(dev, "24m");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (IS_ERR(dp->phy_24m)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_err(dev, "cannot get clock 24m\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return PTR_ERR(dp->phy_24m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = clk_set_rate(dp->phy_24m, 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dp->grf = syscon_node_to_regmap(dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (IS_ERR(dp->grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(dev, "rk3288-dp needs the General Register Files syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return PTR_ERR(dp->grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_err(dev, "failed to create phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) phy_set_drvdata(phy, dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .compatible = "rockchip,rk3288-dp-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct platform_driver rockchip_dp_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .probe = rockchip_dp_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .name = "rockchip-dp-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .of_match_table = rockchip_dp_phy_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) module_platform_driver(rockchip_dp_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MODULE_DESCRIPTION("Rockchip DP PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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