^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip MIPI CSI2 DPHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "phy-rockchip-csi2-dphy-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "phy-rockchip-samsung-dcphy.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct sensor_async_subdev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct v4l2_async_subdev asd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct v4l2_mbus_config mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static LIST_HEAD(csi2dphy_device_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static inline struct csi2_dphy *to_csi2_dphy(struct v4l2_subdev *subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return container_of(subdev, struct csi2_dphy, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct media_pad *local, *remote;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct media_entity *sensor_me;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) local = &sd->entity.pads[CSI2_DPHY_RX_PAD_SINK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) remote = media_entity_remote_pad(local);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (!remote) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) v4l2_warn(sd, "No link between dphy and sensor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) sensor_me = media_entity_remote_pad(local)->entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return media_entity_to_v4l2_subdev(sensor_me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct csi2_sensor *sd_to_sensor(struct csi2_dphy *dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) for (i = 0; i < dphy->num_sensors; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (dphy->sensors[i].sd == sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return &dphy->sensors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int csi2_dphy_get_sensor_data_rate(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct csi2_dphy *dphy = to_csi2_dphy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct v4l2_querymenu qm = { .id = V4L2_CID_LINK_FREQ, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) link_freq = v4l2_ctrl_find(sensor_sd->ctrl_handler, V4L2_CID_LINK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!link_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) v4l2_warn(sd, "No pixel rate control in subdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) qm.index = v4l2_ctrl_g_ctrl(link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = v4l2_querymenu(sensor_sd->ctrl_handler, &qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) v4l2_err(sd, "Failed to get menu item\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!qm.value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) v4l2_err(sd, "Invalid link_freq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dphy->data_rate_mbps = qm.value * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) do_div(dphy->data_rate_mbps, 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) v4l2_info(sd, "dphy%d, data_rate_mbps %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dphy->phy_index, dphy->data_rate_mbps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int csi2_dphy_update_sensor_mbus(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct csi2_dphy *dphy = to_csi2_dphy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct v4l2_mbus_config mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct rkmodule_bus_config bus_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = v4l2_subdev_call(sensor_sd, pad, get_mbus_config, 0, &mbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sensor->mbus = mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) switch (mbus.flags & V4L2_MBUS_CSI2_LANES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case V4L2_MBUS_CSI2_1_LANE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) sensor->lanes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case V4L2_MBUS_CSI2_2_LANE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) sensor->lanes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case V4L2_MBUS_CSI2_3_LANE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) sensor->lanes = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case V4L2_MBUS_CSI2_4_LANE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) sensor->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (dphy->drv_data->vendor == PHY_VENDOR_INNO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = v4l2_subdev_call(sensor_sd, core, ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) RKMODULE_GET_BUS_CONFIG, &bus_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_info(dphy->dev, "phy_mode %d,lane %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bus_config.bus.phy_mode, bus_config.bus.lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (bus_config.bus.phy_mode == PHY_FULL_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (dphy->dphy_hw->drv_data->chip_id == CHIP_ID_RK3588 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dphy->phy_index % 3 == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_err(dphy->dev, "%s dphy%d only use for PHY_SPLIT_23\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __func__, dphy->phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dphy->lane_mode = LANE_MODE_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } else if (bus_config.bus.phy_mode == PHY_SPLIT_01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (dphy->dphy_hw->drv_data->chip_id == CHIP_ID_RK3588_DCPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_err(dphy->dev, "%s The chip not support split mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) } else if (dphy->phy_index % 3 == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(dphy->dev, "%s dphy%d only use for PHY_SPLIT_23\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __func__, dphy->phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dphy->lane_mode = LANE_MODE_SPLIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } else if (bus_config.bus.phy_mode == PHY_SPLIT_23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (dphy->dphy_hw->drv_data->chip_id == CHIP_ID_RK3588_DCPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_err(dphy->dev, "%s The chip not support split mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } else if (dphy->phy_index % 3 != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(dphy->dev, "%s dphy%d not support PHY_SPLIT_23\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) __func__, dphy->phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dphy->lane_mode = LANE_MODE_SPLIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dphy->dphy_hw->lane_mode = dphy->lane_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (dphy->drv_data->vendor == PHY_VENDOR_SAMSUNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = v4l2_subdev_call(sensor_sd, core, ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) RKMODULE_GET_CSI_DPHY_PARAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) &dphy->dphy_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_dbg(dphy->dev, "%s fail to get dphy param, used default value\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int csi2_dphy_s_stream_start(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct csi2_dphy *dphy = to_csi2_dphy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct csi2_dphy_hw *hw = dphy->dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct samsung_mipi_dcphy *samsung_phy = dphy->samsung_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (dphy->is_streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = csi2_dphy_get_sensor_data_rate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) csi2_dphy_update_sensor_mbus(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (dphy->drv_data->vendor == PHY_VENDOR_SAMSUNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (samsung_phy && samsung_phy->stream_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) samsung_phy->stream_on(dphy, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (hw->stream_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) hw->stream_on(dphy, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dphy->is_streaming = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int csi2_dphy_s_stream_stop(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct csi2_dphy *dphy = to_csi2_dphy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct csi2_dphy_hw *hw = dphy->dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct samsung_mipi_dcphy *samsung_phy = dphy->samsung_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!dphy->is_streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (dphy->drv_data->vendor == PHY_VENDOR_SAMSUNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (samsung_phy && samsung_phy->stream_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) samsung_phy->stream_off(dphy, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (hw->stream_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) hw->stream_off(dphy, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dphy->is_streaming = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_info(dphy->dev, "%s stream stop, dphy%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __func__, dphy->phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int csi2_dphy_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct csi2_dphy *dphy = to_csi2_dphy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mutex_lock(&dphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = csi2_dphy_s_stream_start(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = csi2_dphy_s_stream_stop(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mutex_unlock(&dphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_info(dphy->dev, "%s stream on:%d, dphy%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __func__, on, dphy->phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int csi2_dphy_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct v4l2_subdev *sensor = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return v4l2_subdev_call(sensor, video, g_frame_interval, fi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int csi2_dphy_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct csi2_dphy *dphy = to_csi2_dphy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct csi2_sensor *sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!sensor_sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) sensor = sd_to_sensor(dphy, sensor_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) csi2_dphy_update_sensor_mbus(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *config = sensor->mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int csi2_dphy_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct csi2_dphy *dphy = to_csi2_dphy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return pm_runtime_get_sync(dphy->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return pm_runtime_put(dphy->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static __maybe_unused int csi2_dphy_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct media_entity *me = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct csi2_dphy *dphy = to_csi2_dphy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct csi2_dphy_hw *hw = dphy->dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct samsung_mipi_dcphy *samsung_phy = dphy->samsung_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (dphy->drv_data->vendor == PHY_VENDOR_SAMSUNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (samsung_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clk_disable_unprepare(samsung_phy->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) clk_bulk_disable_unprepare(hw->num_clks, hw->clks_bulk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static __maybe_unused int csi2_dphy_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct media_entity *me = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct csi2_dphy *dphy = to_csi2_dphy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct csi2_dphy_hw *hw = dphy->dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct samsung_mipi_dcphy *samsung_phy = dphy->samsung_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (dphy->drv_data->vendor == PHY_VENDOR_SAMSUNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (samsung_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) clk_prepare_enable(samsung_phy->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = clk_bulk_prepare_enable(hw->num_clks, hw->clks_bulk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_err(hw->dev, "failed to enable clks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* dphy accepts all fmt/size from sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int csi2_dphy_get_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct csi2_dphy *dphy = to_csi2_dphy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Do not allow format changes and just relay whatever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * set currently in the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!sensor_sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = v4l2_subdev_call(sensor_sd, pad, get_fmt, NULL, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!ret && fmt->pad == 0 && fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) sensor->format = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int csi2_dphy_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct v4l2_subdev *sensor = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return v4l2_subdev_call(sensor, pad, get_selection, NULL, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct v4l2_subdev_core_ops csi2_dphy_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .s_power = csi2_dphy_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct v4l2_subdev_video_ops csi2_dphy_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .g_frame_interval = csi2_dphy_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .s_stream = csi2_dphy_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct v4l2_subdev_pad_ops csi2_dphy_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .set_fmt = csi2_dphy_get_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .get_fmt = csi2_dphy_get_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .get_selection = csi2_dphy_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .get_mbus_config = csi2_dphy_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct v4l2_subdev_ops csi2_dphy_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .core = &csi2_dphy_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .video = &csi2_dphy_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .pad = &csi2_dphy_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* The .bound() notifier callback when a match is found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) rockchip_csi2_dphy_notifier_bound(struct v4l2_async_notifier *notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct v4l2_async_subdev *asd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct csi2_dphy *dphy = container_of(notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct csi2_dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct sensor_async_subdev *s_asd = container_of(asd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct sensor_async_subdev, asd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct csi2_sensor *sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int pad, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (dphy->num_sensors == ARRAY_SIZE(dphy->sensors))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) sensor = &dphy->sensors[dphy->num_sensors++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) sensor->lanes = s_asd->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) sensor->mbus = s_asd->mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) sensor->sd = sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_info(dphy->dev, "dphy%d matches %s:bus type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dphy->phy_index, sd->name, s_asd->mbus.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) for (pad = 0; pad < sensor->sd->entity.num_pads; pad++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (sensor->sd->entity.pads[pad].flags & MEDIA_PAD_FL_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (pad == sensor->sd->entity.num_pads) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dev_err(dphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "failed to find src pad for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) sensor->sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = media_create_pad_link(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &sensor->sd->entity, pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) &dphy->sd.entity, CSI2_DPHY_RX_PAD_SINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dphy->num_sensors != 1 ? 0 : MEDIA_LNK_FL_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_err(dphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "failed to create link for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) sensor->sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* The .unbind callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) rockchip_csi2_dphy_notifier_unbind(struct v4l2_async_notifier *notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct v4l2_async_subdev *asd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct csi2_dphy *dphy = container_of(notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct csi2_dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct csi2_sensor *sensor = sd_to_sensor(dphy, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) sensor->sd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) v4l2_async_notifier_operations rockchip_csi2_dphy_async_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .bound = rockchip_csi2_dphy_notifier_bound,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .unbind = rockchip_csi2_dphy_notifier_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int rockchip_csi2_dphy_fwnode_parse(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct v4l2_fwnode_endpoint *vep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct v4l2_async_subdev *asd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct sensor_async_subdev *s_asd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) container_of(asd, struct sensor_async_subdev, asd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct v4l2_mbus_config *config = &s_asd->mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (vep->base.port != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_err(dev, "The PHY has only port 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (vep->bus_type == V4L2_MBUS_CSI2_DPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) config->flags = vep->bus.mipi_csi2.flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) } else if (vep->bus_type == V4L2_MBUS_CCP2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) config->type = V4L2_MBUS_CCP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) s_asd->lanes = vep->bus.mipi_csi1.data_lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_err(dev, "Only CSI2 type is currently supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) switch (s_asd->lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) config->flags |= V4L2_MBUS_CSI2_1_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) config->flags |= V4L2_MBUS_CSI2_2_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) config->flags |= V4L2_MBUS_CSI2_3_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) config->flags |= V4L2_MBUS_CSI2_4_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int rockchip_csi2dphy_media_init(struct csi2_dphy *dphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dphy->pads[CSI2_DPHY_RX_PAD_SOURCE].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dphy->pads[CSI2_DPHY_RX_PAD_SINK].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dphy->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = media_entity_pads_init(&dphy->sd.entity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) CSI2_DPHY_RX_PADS_NUM, dphy->pads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) v4l2_async_notifier_init(&dphy->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dphy->dev, &dphy->notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sizeof(struct sensor_async_subdev), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) rockchip_csi2_dphy_fwnode_parse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dphy->sd.subdev_notifier = &dphy->notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dphy->notifier.ops = &rockchip_csi2_dphy_async_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = v4l2_async_subdev_notifier_register(&dphy->sd, &dphy->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_err(dphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) "failed to register async notifier : %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) v4l2_async_notifier_cleanup(&dphy->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return v4l2_async_register_subdev(&dphy->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int rockchip_csi2_dphy_attach_samsung_phy(struct csi2_dphy *dphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct device *dev = dphy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct phy *dcphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct samsung_mipi_dcphy *dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dcphy = devm_phy_optional_get(dev, "dcphy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (IS_ERR(dcphy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = PTR_ERR(dcphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(dphy->dev, "failed to get mipi dcphy: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dphy_hw = phy_get_drvdata(dcphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dphy_hw->dphy_dev[dphy_hw->dphy_dev_num] = dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dphy_hw->dphy_dev_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dphy->samsung_phy = dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int rockchip_csi2_dphy_detach_samsung_phy(struct csi2_dphy *dphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct samsung_mipi_dcphy *dphy_hw = dphy->samsung_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct csi2_dphy *csi2_dphy = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) for (i = 0; i < dphy_hw->dphy_dev_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) csi2_dphy = dphy_hw->dphy_dev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (csi2_dphy &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) csi2_dphy->phy_index == dphy->phy_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dphy_hw->dphy_dev[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dphy_hw->dphy_dev_num--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int rockchip_csi2_dphy_attach_hw(struct csi2_dphy *dphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct platform_device *plat_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct device *dev = dphy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct csi2_dphy_hw *dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) enum csi2_dphy_lane_mode target_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (dphy->phy_index % 3 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) target_mode = LANE_MODE_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) target_mode = LANE_MODE_SPLIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) np = of_parse_phandle(dev->of_node, "rockchip,hw", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!np || !of_device_is_available(np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dev_err(dphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) "failed to get dphy%d hw node\n", dphy->phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) plat_dev = of_find_device_by_node(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (!plat_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dev_err(dphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "failed to get dphy%d hw from node\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dphy->phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dphy_hw = platform_get_drvdata(plat_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (!dphy_hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_err(dphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "failed attach dphy%d hw\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dphy->phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (dphy_hw->lane_mode == LANE_MODE_UNDEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dphy_hw->lane_mode = target_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct csi2_dphy *phy = dphy_hw->dphy_dev[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) for (i = 0; i < dphy_hw->dphy_dev_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (dphy_hw->dphy_dev[i]->lane_mode == dphy_hw->lane_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) phy = dphy_hw->dphy_dev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (target_mode != dphy_hw->lane_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_err(dphy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "Err:csi2 dphy hw has been set as %s mode by phy%d, target mode is:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dphy_hw->lane_mode == LANE_MODE_FULL ? "full" : "split",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) phy->phy_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) target_mode == LANE_MODE_FULL ? "full" : "split");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dphy_hw->dphy_dev[dphy_hw->dphy_dev_num] = dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dphy_hw->dphy_dev_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dphy->dphy_hw = dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int rockchip_csi2_dphy_detach_hw(struct csi2_dphy *dphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct csi2_dphy_hw *dphy_hw = dphy->dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct csi2_dphy *csi2_dphy = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) for (i = 0; i < dphy_hw->dphy_dev_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) csi2_dphy = dphy_hw->dphy_dev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (csi2_dphy &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) csi2_dphy->phy_index == dphy->phy_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dphy_hw->dphy_dev[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dphy_hw->dphy_dev_num--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static struct dphy_drv_data rk3568_dphy_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .dev_name = "csi2dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .vendor = PHY_VENDOR_INNO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static struct dphy_drv_data rk3588_dcphy_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .dev_name = "csi2dcphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .vendor = PHY_VENDOR_SAMSUNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .vendor = PHY_VENDOR_SAMSUNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .lp_vol_ref = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .lp_hys_sw = {3, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .lp_escclk_pol_sel = {1, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .skew_data_cal_clk = {0, 3, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .clk_hs_term_sel = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .data_hs_term_sel = {2, 2, 2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .reserved = {0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static struct dphy_drv_data rv1106_dphy_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .dev_name = "csi2dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .vendor = PHY_VENDOR_INNO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const struct of_device_id rockchip_csi2_dphy_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .compatible = "rockchip,rk3568-csi2-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .data = &rk3568_dphy_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .compatible = "rockchip,rk3588-csi2-dcphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .data = &rk3588_dcphy_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .compatible = "rockchip,rv1106-csi2-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .data = &rv1106_dphy_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MODULE_DEVICE_TABLE(of, rockchip_csi2_dphy_match_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int rockchip_csi2_dphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct csi2_dphy *csi2dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) const struct dphy_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) csi2dphy = devm_kzalloc(dev, sizeof(*csi2dphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!csi2dphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) csi2dphy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) of_id = of_match_device(rockchip_csi2_dphy_match_id, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) drv_data = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) csi2dphy->drv_data = drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) csi2dphy->phy_index = of_alias_get_id(dev->of_node, drv_data->dev_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (csi2dphy->phy_index < 0 || csi2dphy->phy_index >= PHY_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) csi2dphy->phy_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (csi2dphy->drv_data->vendor == PHY_VENDOR_SAMSUNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = rockchip_csi2_dphy_attach_samsung_phy(csi2dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) csi2dphy->dphy_param = rk3588_dcphy_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = rockchip_csi2_dphy_attach_hw(csi2dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) "csi2 dphy hw can't be attached, register dphy%d failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) csi2dphy->phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) sd = &csi2dphy->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mutex_init(&csi2dphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) v4l2_subdev_init(sd, &csi2_dphy_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) snprintf(sd->name, sizeof(sd->name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) "rockchip-csi2-dphy%d", csi2dphy->phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) sd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) platform_set_drvdata(pdev, &sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = rockchip_csi2dphy_media_init(csi2dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) goto detach_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_info(dev, "csi2 dphy%d probe successfully!\n", csi2dphy->phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) detach_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mutex_destroy(&csi2dphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (csi2dphy->drv_data->vendor == PHY_VENDOR_SAMSUNG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) rockchip_csi2_dphy_detach_samsung_phy(csi2dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) rockchip_csi2_dphy_detach_hw(csi2dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int rockchip_csi2_dphy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct media_entity *me = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct csi2_dphy *dphy = to_csi2_dphy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mutex_destroy(&dphy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static const struct dev_pm_ops rockchip_csi2_dphy_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) SET_RUNTIME_PM_OPS(csi2_dphy_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) csi2_dphy_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct platform_driver rockchip_csi2_dphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .probe = rockchip_csi2_dphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .remove = rockchip_csi2_dphy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .name = "rockchip-csi2-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .pm = &rockchip_csi2_dphy_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .of_match_table = rockchip_csi2_dphy_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int __init rockchip_csi2_dphy_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return platform_driver_register(&rockchip_csi2_dphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) subsys_initcall(rockchip_csi2_dphy_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) module_platform_driver(rockchip_csi2_dphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) MODULE_AUTHOR("Rockchip Camera/ISP team");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) MODULE_DESCRIPTION("Rockchip MIPI CSI2 DPHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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