^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip MIPI CSI2 DPHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "phy-rockchip-csi2-dphy-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* GRF REG OFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GRF_VI_CON0 (0x0340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GRF_VI_CON1 (0x0344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*RK3588 DPHY GRF REG OFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GRF_DPHY_CON0 (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GRF_SOC_CON2 (0x0308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*RV1106 DPHY GRF REG OFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GRF_VI_MISC_CON0 (0x50000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GRF_VI_CSIPHY_CON5 (0x50014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*GRF REG BIT DEFINE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GRF_CSI2PHY_LANE_SEL_SPLIT (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GRF_CSI2PHY_SEL_SPLIT_0_1 (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GRF_CSI2PHY_SEL_SPLIT_2_3 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* PHY REG OFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CSI2_DPHY_CTRL_INVALID_OFFSET (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CSI2_DPHY_CTRL_PWRCTL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CSI2_DPHY_CTRL_INVALID_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CSI2_DPHY_CTRL_LANE_ENABLE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CSI2_DPHY_CLK1_LANE_EN (0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CSI2_DPHY_DUAL_CAL_EN (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CSI2_DPHY_CLK_INV (0X84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CSI2_DPHY_CLK_WR_THS_SETTLE (0x160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CSI2_DPHY_CLK_CALIB_EN (0x168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CSI2_DPHY_LANE0_WR_THS_SETTLE (0x1e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CSI2_DPHY_LANE0_CALIB_EN (0x1e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CSI2_DPHY_LANE1_WR_THS_SETTLE (0x260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CSI2_DPHY_LANE1_CALIB_EN (0x268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CSI2_DPHY_LANE2_WR_THS_SETTLE (0x2e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CSI2_DPHY_LANE2_CALIB_EN (0x2e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CSI2_DPHY_LANE3_WR_THS_SETTLE (0x360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CSI2_DPHY_LANE3_CALIB_EN (0x368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CSI2_DPHY_CLK1_WR_THS_SETTLE (0x3e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CSI2_DPHY_CLK1_CALIB_EN (0x3e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CSI2_DPHY_PATH0_MODE_SEL (0x44C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CSI2_DPHY_PATH0_LVDS_MODE_SEL (0x480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CSI2_DPHY_PATH1_MODE_SEL (0x84C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CSI2_DPHY_PATH1_LVDS_MODE_SEL (0x880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* PHY REG BIT DEFINE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CSI2_DPHY_LANE_MODE_FULL (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CSI2_DPHY_LANE_MODE_SPLIT (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CSI2_DPHY_LANE_SPLIT_TOP (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CSI2_DPHY_LANE_SPLIT_BOT (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CSI2_DPHY_LANE_SPLIT_LANE0_1 (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CSI2_DPHY_LANE_SPLIT_LANE2_3 (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CSI2_DPHY_LANE_DUAL_MODE_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CSI2_DPHY_LANE_PARA_ARR_NUM (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum csi2_dphy_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DPHY0 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DPHY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DPHY2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum csi2_dphy_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) CSI2_DPHY_LANE_CLOCK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) CSI2_DPHY_LANE_CLOCK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) CSI2_DPHY_LANE_DATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) CSI2_DPHY_LANE_DATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CSI2_DPHY_LANE_DATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CSI2_DPHY_LANE_DATA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enum grf_reg_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) GRF_DPHY_RX0_TURNDISABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) GRF_DPHY_RX0_FORCERXMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) GRF_DPHY_RX0_FORCETXSTOPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) GRF_DPHY_RX0_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) GRF_DPHY_RX0_TESTCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GRF_DPHY_RX0_TESTCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) GRF_DPHY_RX0_TESTEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) GRF_DPHY_RX0_TESTDIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) GRF_DPHY_RX0_TURNREQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) GRF_DPHY_RX0_TESTDOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) GRF_DPHY_TX0_TURNDISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) GRF_DPHY_TX0_FORCERXMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) GRF_DPHY_TX0_FORCETXSTOPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) GRF_DPHY_TX0_TURNREQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) GRF_DPHY_TX1RX1_TURNDISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) GRF_DPHY_TX1RX1_FORCERXMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) GRF_DPHY_TX1RX1_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) GRF_DPHY_TX1RX1_MASTERSLAVEZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) GRF_DPHY_TX1RX1_BASEDIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) GRF_DPHY_TX1RX1_ENABLECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) GRF_DPHY_TX1RX1_TURNREQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GRF_DPHY_RX1_SRC_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* rk3288 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) GRF_CON_DISABLE_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) GRF_CON_ISP_DPHY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) GRF_DSI_CSI_TESTBUS_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) GRF_DVP_V18SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* rk1808 & rk3326 & rv1126 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) GRF_DPHY_CSI2PHY_FORCERXMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) GRF_DPHY_CSI2PHY_CLKLANE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) GRF_DPHY_CSI2PHY_DATALANE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* rv1126 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) GRF_DPHY_CLK_INV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) GRF_DPHY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* rk3368 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) GRF_ISP_MIPI_CSI_HOST_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* below is for rk3399 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) GRF_DPHY_RX0_CLK_INV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) GRF_DPHY_RX1_CLK_INV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) GRF_DPHY_TX1RX1_SRC_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* below is for rk3568 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) GRF_DPHY_CSI2PHY_CLKLANE1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) GRF_DPHY_CLK1_INV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) GRF_DPHY_ISP_CSI2PHY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) GRF_DPHY_CIF_CSI2PHY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) GRF_DPHY_CSI2PHY_LANE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) GRF_DPHY_CSI2PHY1_LANE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) GRF_DPHY_CSI2PHY_DATALANE_EN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) GRF_DPHY_CSI2PHY_DATALANE_EN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) GRF_CPHY_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) GRF_DPHY_CSIHOST2_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) GRF_DPHY_CSIHOST3_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) GRF_DPHY_CSIHOST4_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) GRF_DPHY_CSIHOST5_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* below is for rv1106 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) GRF_MIPI_HOST0_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) GRF_LVDS_HOST0_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum csi2dphy_reg_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) CSI2PHY_REG_CTRL_LANE_ENABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CSI2PHY_CTRL_PWRCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CSI2PHY_CTRL_DIG_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CSI2PHY_CLK_THS_SETTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CSI2PHY_LANE0_THS_SETTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CSI2PHY_LANE1_THS_SETTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) CSI2PHY_LANE2_THS_SETTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) CSI2PHY_LANE3_THS_SETTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) CSI2PHY_CLK_CALIB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CSI2PHY_LANE0_CALIB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CSI2PHY_LANE1_CALIB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CSI2PHY_LANE2_CALIB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CSI2PHY_LANE3_CALIB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) //rv1126 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CSI2PHY_MIPI_LVDS_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CSI2PHY_LVDS_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) //rk3568 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CSI2PHY_DUAL_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) CSI2PHY_CLK1_THS_SETTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CSI2PHY_CLK1_CALIB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) //rk3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CSI2PHY_CLK_LANE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) CSI2PHY_CLK1_LANE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) CSI2PHY_DATA_LANE0_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CSI2PHY_DATA_LANE1_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) CSI2PHY_DATA_LANE2_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) CSI2PHY_DATA_LANE3_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) CSI2PHY_LANE0_ERR_SOT_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) CSI2PHY_LANE1_ERR_SOT_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CSI2PHY_LANE2_ERR_SOT_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) CSI2PHY_LANE3_ERR_SOT_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CSI2PHY_S0C_GNR_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CSI2PHY_COMBO_S0D0_GNR_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CSI2PHY_COMBO_S0D1_GNR_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CSI2PHY_COMBO_S0D2_GNR_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CSI2PHY_S0D3_GNR_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CSI2PHY_PATH0_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CSI2PHY_PATH0_LVDS_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CSI2PHY_PATH1_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CSI2PHY_PATH1_LVDS_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CSI2PHY_CLK_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HIWORD_UPDATE(val, mask, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ((val) << (shift) | (mask) << ((shift) + 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GRF_REG(_offset, _width, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CSI2PHY_REG(_offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .offset = _offset, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct hsfreq_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 range_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u16 cfg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static inline void write_sys_grf_reg(struct csi2_dphy_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int index, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const struct grf_reg *reg = &hw->grf_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (reg->mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) regmap_write(hw->regmap_sys_grf, reg->offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static inline void write_grf_reg(struct csi2_dphy_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int index, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) const struct grf_reg *reg = &hw->grf_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (reg->mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) regmap_write(hw->regmap_grf, reg->offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline u32 read_grf_reg(struct csi2_dphy_hw *hw, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) const struct grf_reg *reg = &hw->grf_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (reg->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) regmap_read(hw->regmap_grf, reg->offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) val = (val >> reg->shift) & reg->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static inline void write_csi2_dphy_reg(struct csi2_dphy_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int index, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) (index == CSI2PHY_CLK_LANE_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) (index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) reg->offset != 0x0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) writel(value, hw->hw_base_addr + reg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline void write_csi2_dphy_reg_mask(struct csi2_dphy_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int index, u32 value, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 read_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) read_val = readl(hw->hw_base_addr + reg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) read_val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) read_val |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) writel(read_val, hw->hw_base_addr + reg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static inline void read_csi2_dphy_reg(struct csi2_dphy_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int index, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) (index == CSI2PHY_CLK_LANE_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) (index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) reg->offset != 0x0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *value = readl(hw->hw_base_addr + reg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int hsfreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) enum csi2_dphy_lane lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) switch (lane) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case CSI2_DPHY_LANE_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) offset = CSI2PHY_CLK_THS_SETTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case CSI2_DPHY_LANE_CLOCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) offset = CSI2PHY_CLK1_THS_SETTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case CSI2_DPHY_LANE_DATA0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) offset = CSI2PHY_LANE0_THS_SETTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case CSI2_DPHY_LANE_DATA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) offset = CSI2PHY_LANE1_THS_SETTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case CSI2_DPHY_LANE_DATA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) offset = CSI2PHY_LANE2_THS_SETTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case CSI2_DPHY_LANE_DATA3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) offset = CSI2PHY_LANE3_THS_SETTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) read_csi2_dphy_reg(hw, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) val = (val & ~0x7f) | hsfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) write_csi2_dphy_reg(hw, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct grf_reg rk3568_grf_dphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CON0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CON0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_VI_CON0, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_VI_CON0, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CON0, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CON0, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [GRF_DPHY_ISP_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [GRF_DPHY_CIF_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_VI_CON1, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct csi2dphy_reg rk3568_csi2dphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct grf_reg rk3588_grf_dphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_DPHY_CON0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_DPHY_CON0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_DPHY_CON0, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_DPHY_CON0, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_DPHY_CON0, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_DPHY_CON0, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) [GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) [GRF_DPHY_CSIHOST2_SEL] = GRF_REG(GRF_SOC_CON2, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) [GRF_DPHY_CSIHOST3_SEL] = GRF_REG(GRF_SOC_CON2, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) [GRF_DPHY_CSIHOST4_SEL] = GRF_REG(GRF_SOC_CON2, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) [GRF_DPHY_CSIHOST5_SEL] = GRF_REG(GRF_SOC_CON2, 1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct csi2dphy_reg rk3588_csi2dphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct grf_reg rv1106_grf_dphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CSIPHY_CON5, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_VI_CSIPHY_CON5, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_VI_CSIPHY_CON5, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) [GRF_MIPI_HOST0_SEL] = GRF_REG(GRF_VI_MISC_CON0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) [GRF_LVDS_HOST0_SEL] = GRF_REG(GRF_VI_MISC_CON0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const struct csi2dphy_reg rv1106_csi2dphy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) [CSI2PHY_PATH0_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH0_MODE_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [CSI2PHY_PATH0_LVDS_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH0_LVDS_MODE_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) [CSI2PHY_PATH1_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH1_MODE_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [CSI2PHY_PATH1_LVDS_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH1_LVDS_MODE_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [CSI2PHY_CLK_INV] = CSI2PHY_REG(CSI2_DPHY_CLK_INV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* These tables must be sorted by .range_h ascending. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const struct hsfreq_range rk3568_csi2_dphy_hw_hsfreq_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct media_pad *local, *remote;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct media_entity *sensor_me;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) local = &sd->entity.pads[CSI2_DPHY_RX_PAD_SINK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) remote = media_entity_remote_pad(local);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!remote) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) v4l2_warn(sd, "No link between dphy and sensor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) sensor_me = media_entity_remote_pad(local)->entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return media_entity_to_v4l2_subdev(sensor_me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct csi2_sensor *sd_to_sensor(struct csi2_dphy *dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for (i = 0; i < dphy->num_sensors; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (dphy->sensors[i].sd == sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return &dphy->sensors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static unsigned char get_lvds_data_width(u32 pixelformat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) switch (pixelformat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* csi raw8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case MEDIA_BUS_FMT_SBGGR8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case MEDIA_BUS_FMT_SGBRG8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case MEDIA_BUS_FMT_SGRBG8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case MEDIA_BUS_FMT_SRGGB8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* csi raw10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case MEDIA_BUS_FMT_SBGGR10_1X10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case MEDIA_BUS_FMT_SGBRG10_1X10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case MEDIA_BUS_FMT_SGRBG10_1X10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case MEDIA_BUS_FMT_SRGGB10_1X10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* csi raw12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case MEDIA_BUS_FMT_SBGGR12_1X12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case MEDIA_BUS_FMT_SGBRG12_1X12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case MEDIA_BUS_FMT_SGRBG12_1X12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case MEDIA_BUS_FMT_SRGGB12_1X12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* csi uyvy 422 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case MEDIA_BUS_FMT_VYUY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case MEDIA_BUS_FMT_YUYV8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case MEDIA_BUS_FMT_YVYU8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case MEDIA_BUS_FMT_RGB888_1X24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void csi2_dphy_hw_do_reset(struct csi2_dphy_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (hw->rsts_bulk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) reset_control_assert(hw->rsts_bulk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (hw->rsts_bulk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) reset_control_deassert(hw->rsts_bulk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct csi2_sensor *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct csi2_dphy_hw *hw = dphy->dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct v4l2_subdev *sd = &dphy->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) bool is_cif = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) char *model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) model = sd->v4l2_dev->mdev->model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (!strncmp(model, "rkcif_mipi_lvds", sizeof("rkcif_mipi_lvds") - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) is_cif = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) is_cif = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (hw->lane_mode == LANE_MODE_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) val = ~GRF_CSI2PHY_LANE_SEL_SPLIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (dphy->phy_index < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GENMASK(sensor->lanes - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (hw->drv_data->chip_id < CHIP_ID_RK3588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GENMASK(sensor->lanes - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (hw->drv_data->chip_id < CHIP_ID_RK3588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) val = GRF_CSI2PHY_LANE_SEL_SPLIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) switch (dphy->phy_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GENMASK(sensor->lanes - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (is_cif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) GRF_CSI2PHY_SEL_SPLIT_0_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GRF_CSI2PHY_SEL_SPLIT_0_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) } else if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) write_sys_grf_reg(hw, GRF_DPHY_CSIHOST2_SEL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) } else if (hw->drv_data->chip_id == CHIP_ID_RV1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) write_grf_reg(hw, GRF_MIPI_HOST0_SEL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) write_grf_reg(hw, GRF_LVDS_HOST0_SEL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GENMASK(sensor->lanes - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (is_cif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GRF_CSI2PHY_SEL_SPLIT_2_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) GRF_CSI2PHY_SEL_SPLIT_2_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) } else if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) write_sys_grf_reg(hw, GRF_DPHY_CSIHOST3_SEL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) write_sys_grf_reg(hw, GRF_DPHY_CSIHOST4_SEL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GENMASK(sensor->lanes - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) write_sys_grf_reg(hw, GRF_DPHY_CSIHOST5_SEL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) GENMASK(sensor->lanes - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int csi2_dphy_hw_stream_on(struct csi2_dphy *dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct csi2_dphy_hw *hw = dphy->dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) const struct dphy_hw_drv_data *drv_data = hw->drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int i, hsfreq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u32 val = 0, pre_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u8 lvds_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mutex_lock(&hw->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* set data lane num and enable clock lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * for rk356x: dphy0 is used just for full mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * dphy1 is used just for split mode,uses lane0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * dphy2 is used just for split mode,uses lane2_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) read_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, &pre_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (hw->lane_mode == LANE_MODE_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) val |= (GENMASK(sensor->lanes - 1, 0) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (dphy->phy_index % 3 == DPHY1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) val |= (GENMASK(sensor->lanes - 1, 0) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (dphy->phy_index % 3 == DPHY2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) val |= (GENMASK(sensor->lanes - 1, 0) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (hw->drv_data->chip_id >= CHIP_ID_RK3588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) val |= pre_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Reset dphy digital part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (hw->lane_mode == LANE_MODE_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) read_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (!(val & CSI2_DPHY_LANE_DUAL_MODE_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) csi2_dphy_config_dual_mode(dphy, sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* not into receive mode/wait stopstate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) write_grf_reg(hw, GRF_DPHY_CSI2PHY_FORCERXMODE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* enable calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (dphy->data_rate_mbps > 1500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (hw->lane_mode == LANE_MODE_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (sensor->lanes > 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (sensor->lanes > 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (sensor->lanes > 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (sensor->lanes > 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (dphy->phy_index % 3 == DPHY1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (sensor->lanes > 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (sensor->lanes > 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (dphy->phy_index % 3 == DPHY2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) write_csi2_dphy_reg(hw, CSI2PHY_CLK1_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (sensor->lanes > 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (sensor->lanes > 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* set clock lane and data lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) for (i = 0; i < num_hsfreq_ranges; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (hsfreq_ranges[i].range_h >= dphy->data_rate_mbps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) hsfreq = hsfreq_ranges[i].cfg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (i == num_hsfreq_ranges) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) i = num_hsfreq_ranges - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_warn(dphy->dev, "data rate: %lld mbps, max support %d mbps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dphy->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) hsfreq = hsfreq_ranges[i].cfg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (hw->lane_mode == LANE_MODE_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (sensor->lanes > 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (sensor->lanes > 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (sensor->lanes > 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (sensor->lanes > 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (dphy->phy_index % 3 == DPHY1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (dphy->phy_index % 3 == DPHY2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (hw->drv_data->chip_id == CHIP_ID_RV1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (dphy->phy_index % 3 == DPHY0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dphy->phy_index % 3 == DPHY1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) lvds_width = get_lvds_data_width(sensor->format.code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) write_csi2_dphy_reg(hw, CSI2PHY_PATH0_LVDS_MODEL, (lvds_width << 4) | 0X0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) lvds_width = get_lvds_data_width(sensor->format.code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) write_csi2_dphy_reg(hw, CSI2PHY_PATH1_LVDS_MODEL, (lvds_width << 4) | 0X0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (hw->lane_mode == LANE_MODE_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) write_csi2_dphy_reg(hw, CSI2PHY_CLK_INV, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) write_csi2_dphy_reg(hw, CSI2PHY_CLK_INV, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) atomic_inc(&hw->stream_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) mutex_unlock(&hw->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static int csi2_dphy_hw_stream_off(struct csi2_dphy *dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct csi2_dphy_hw *hw = dphy->dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (atomic_dec_return(&hw->stream_cnt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mutex_lock(&hw->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) csi2_dphy_hw_do_reset(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) mutex_unlock(&hw->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int csi2_dphy_hw_ttl_mode_enable(struct csi2_dphy_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = clk_bulk_prepare_enable(hw->num_clks, hw->clks_bulk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_err(hw->dev, "failed to enable clks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x7d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static void csi2_dphy_hw_ttl_mode_disable(struct csi2_dphy_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) clk_bulk_disable_unprepare(hw->num_clks, hw->clks_bulk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static void rk3568_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) hw->grf_regs = rk3568_grf_dphy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static void rk3588_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) hw->grf_regs = rk3588_grf_dphy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static void rv1106_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) hw->grf_regs = rv1106_grf_dphy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const struct dphy_hw_drv_data rk3568_csi2_dphy_hw_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .csi2dphy_regs = rk3568_csi2dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .grf_regs = rk3568_grf_dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .individual_init = rk3568_csi2_dphy_hw_individual_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .chip_id = CHIP_ID_RK3568,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .stream_on = csi2_dphy_hw_stream_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .stream_off = csi2_dphy_hw_stream_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const struct dphy_hw_drv_data rk3588_csi2_dphy_hw_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .csi2dphy_regs = rk3588_csi2dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .grf_regs = rk3588_grf_dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .individual_init = rk3588_csi2_dphy_hw_individual_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .chip_id = CHIP_ID_RK3588,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .stream_on = csi2_dphy_hw_stream_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .stream_off = csi2_dphy_hw_stream_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static const struct dphy_hw_drv_data rv1106_csi2_dphy_hw_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .csi2dphy_regs = rv1106_csi2dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .grf_regs = rv1106_grf_dphy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .individual_init = rv1106_csi2_dphy_hw_individual_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .chip_id = CHIP_ID_RV1106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .stream_on = csi2_dphy_hw_stream_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .stream_off = csi2_dphy_hw_stream_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static const struct of_device_id rockchip_csi2_dphy_hw_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .compatible = "rockchip,rk3568-csi2-dphy-hw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .data = &rk3568_csi2_dphy_hw_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .compatible = "rockchip,rk3588-csi2-dphy-hw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .data = &rk3588_csi2_dphy_hw_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .compatible = "rockchip,rv1106-csi2-dphy-hw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .data = &rv1106_csi2_dphy_hw_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) MODULE_DEVICE_TABLE(of, rockchip_csi2_dphy_hw_match_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static int rockchip_csi2_dphy_hw_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct csi2_dphy_hw *dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) const struct dphy_hw_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dphy_hw = devm_kzalloc(dev, sizeof(*dphy_hw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!dphy_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dphy_hw->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) of_id = of_match_device(rockchip_csi2_dphy_hw_match_id, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) drv_data = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) grf = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev_err(dev, "Can't find GRF syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dphy_hw->regmap_grf = grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (drv_data->chip_id == CHIP_ID_RK3588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) grf = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) "rockchip,sys_grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev_err(dev, "Can't find SYS GRF syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dphy_hw->regmap_sys_grf = grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dphy_hw->num_clks = devm_clk_bulk_get_all(dev, &dphy_hw->clks_bulk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (dphy_hw->num_clks < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev_err(dev, "failed to get csi2 clks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dphy_hw->rsts_bulk = devm_reset_control_array_get_optional_exclusive(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (IS_ERR(dphy_hw->rsts_bulk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dev_err_probe(dev, PTR_ERR(dphy_hw->rsts_bulk), "failed to get dphy reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dphy_hw->dphy_dev_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dphy_hw->drv_data = drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dphy_hw->lane_mode = LANE_MODE_UNDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dphy_hw->grf_regs = drv_data->grf_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dphy_hw->txrx_regs = drv_data->txrx_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dphy_hw->csi2dphy_regs = drv_data->csi2dphy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dphy_hw->hw_base_addr = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (IS_ERR(dphy_hw->hw_base_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) resource_size_t offset = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) resource_size_t size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dphy_hw->hw_base_addr = devm_ioremap(dev, offset, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (IS_ERR(dphy_hw->hw_base_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) dev_err(dev, "Can't find csi2 dphy hw addr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) dphy_hw->stream_on = drv_data->stream_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dphy_hw->stream_off = drv_data->stream_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (drv_data->chip_id == CHIP_ID_RV1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dphy_hw->ttl_mode_enable = csi2_dphy_hw_ttl_mode_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dphy_hw->ttl_mode_disable = csi2_dphy_hw_ttl_mode_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dphy_hw->ttl_mode_enable = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dphy_hw->ttl_mode_disable = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) atomic_set(&dphy_hw->stream_cnt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) mutex_init(&dphy_hw->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) platform_set_drvdata(pdev, dphy_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_info(dev, "csi2 dphy hw probe successfully!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static int rockchip_csi2_dphy_hw_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct csi2_dphy_hw *hw = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) mutex_destroy(&hw->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static struct platform_driver rockchip_csi2_dphy_hw_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .probe = rockchip_csi2_dphy_hw_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .remove = rockchip_csi2_dphy_hw_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .name = "rockchip-csi2-dphy-hw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .of_match_table = rockchip_csi2_dphy_hw_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int __init rockchip_csi2_dphy_hw_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return platform_driver_register(&rockchip_csi2_dphy_hw_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) subsys_initcall(rockchip_csi2_dphy_hw_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) module_platform_driver(rockchip_csi2_dphy_hw_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) MODULE_AUTHOR("Rockchip Camera/ISP team");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) MODULE_DESCRIPTION("Rockchip MIPI CSI2 DPHY HW driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags