^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip MIPI CSI2 DPHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PHY_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MAX_DEV_NAME_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* add new chip id in tail by time order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum csi2_dphy_chip_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) CHIP_ID_RK3568 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) CHIP_ID_RK3588 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) CHIP_ID_RK3588_DCPHY = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) CHIP_ID_RV1106 = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum csi2_dphy_rx_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) CSI2_DPHY_RX_PAD_SINK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) CSI2_DPHY_RX_PAD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) CSI2_DPHY_RX_PADS_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum csi2_dphy_lane_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) LANE_MODE_UNDEF = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) LANE_MODE_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) LANE_MODE_SPLIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct grf_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct csi2dphy_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MAX_DPHY_SENSORS (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAX_NUM_CSI2_DPHY (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct csi2_sensor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct v4l2_mbus_config mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct v4l2_mbus_framefmt format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct csi2_dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct samsung_mipi_dcphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct dphy_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const char dev_name[MAX_DEV_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum csi2_dphy_vendor vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct csi2_dphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct csi2_dphy_hw *dphy_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct samsung_mipi_dcphy *samsung_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct v4l2_async_notifier notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct mutex mutex; /* lock for updating protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct media_pad pads[CSI2_DPHY_RX_PADS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct csi2_sensor sensors[MAX_DPHY_SENSORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u64 data_rate_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int num_sensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int phy_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bool is_streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enum csi2_dphy_lane_mode lane_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const struct dphy_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct rkmodule_csi_dphy_param dphy_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct dphy_hw_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) const struct hsfreq_range *hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int num_hsfreq_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const struct hsfreq_range *hsfreq_ranges_cphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int num_hsfreq_ranges_cphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const struct grf_reg *grf_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct txrx_reg *txrx_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const struct csi2dphy_reg *csi2dphy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void (*individual_init)(struct csi2_dphy_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum csi2_dphy_chip_id chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct csi2_dphy_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct regmap *regmap_grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct regmap *regmap_sys_grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const struct grf_reg *grf_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const struct txrx_reg *txrx_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct csi2dphy_reg *csi2dphy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const struct dphy_hw_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void __iomem *hw_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk_bulk_data *clks_bulk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct reset_control *rsts_bulk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct mutex mutex; /* lock for updating protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) atomic_t stream_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int num_sensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int dphy_dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum csi2_dphy_lane_mode lane_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int (*ttl_mode_enable)(struct csi2_dphy_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void (*ttl_mode_disable)(struct csi2_dphy_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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