^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas R-Car Gen2 PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2019 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USBHS_LPSTS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USBHS_UGCTRL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define USBHS_UGCTRL2 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define USBHS_UGSTS 0x88 /* From technical update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Low Power Status register (LPSTS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define USBHS_LPSTS_SUSPM 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* USB General control register (UGCTRL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define USBHS_UGCTRL_CONNECT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define USBHS_UGCTRL_PLLRESET 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* USB General control register 2 (UGCTRL2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define USBHS_UGCTRL2_USB2SEL 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define USBHS_UGCTRL2_USB2SEL_PCI 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define USBHS_UGCTRL2_USB2SEL_USB30 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define USBHS_UGCTRL2_USB0SEL 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define USBHS_UGCTRL2_USB0SEL_PCI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define USBHS_UGCTRL2_USB0SEL_HS_USB 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define USBHS_UGCTRL2_USB0SEL_USB20 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USBHS_UGCTRL2_USB0SEL_HS_USB20 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* USB General status register (UGSTS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define USBHS_UGSTS_LOCK 0x00000100 /* From technical update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PHYS_PER_CHANNEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct rcar_gen2_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct rcar_gen2_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 select_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct rcar_gen2_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct rcar_gen2_phy_driver *drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct rcar_gen2_phy phys[PHYS_PER_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int selected_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 select_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct rcar_gen2_phy_driver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct rcar_gen2_channel *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct rcar_gen2_phy_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const struct phy_ops *gen2_phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const u32 (*select_value)[PHYS_PER_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const u32 num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int rcar_gen2_phy_init(struct phy *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct rcar_gen2_phy *phy = phy_get_drvdata(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct rcar_gen2_channel *channel = phy->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct rcar_gen2_phy_driver *drv = channel->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 ugctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Try to acquire exclusive access to PHY. The first driver calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * phy_init() on a given channel wins, and all attempts to use another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * PHY on this channel will fail until phy_exit() is called by the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * driver. Achieving this with cmpxcgh() should be SMP-safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (cmpxchg(&channel->selected_phy, -1, phy->number) != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clk_prepare_enable(drv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) spin_lock_irqsave(&drv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ugctrl2 = readl(drv->base + USBHS_UGCTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ugctrl2 &= ~channel->select_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ugctrl2 |= phy->select_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel(ugctrl2, drv->base + USBHS_UGCTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) spin_unlock_irqrestore(&drv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int rcar_gen2_phy_exit(struct phy *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct rcar_gen2_phy *phy = phy_get_drvdata(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct rcar_gen2_channel *channel = phy->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clk_disable_unprepare(channel->drv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) channel->selected_phy = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int rcar_gen2_phy_power_on(struct phy *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct rcar_gen2_phy *phy = phy_get_drvdata(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct rcar_gen2_phy_driver *drv = phy->channel->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void __iomem *base = drv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int err = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Skip if it's not USBHS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) spin_lock_irqsave(&drv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Power on USBHS PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) value = readl(base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) value &= ~USBHS_UGCTRL_PLLRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(value, base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) value = readw(base + USBHS_LPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) value |= USBHS_LPSTS_SUSPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) writew(value, base + USBHS_LPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) for (i = 0; i < 20; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) value = readl(base + USBHS_UGSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if ((value & USBHS_UGSTS_LOCK) == USBHS_UGSTS_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) value = readl(base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) value |= USBHS_UGCTRL_CONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(value, base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Timed out waiting for the PLL lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spin_unlock_irqrestore(&drv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int rcar_gen2_phy_power_off(struct phy *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct rcar_gen2_phy *phy = phy_get_drvdata(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct rcar_gen2_phy_driver *drv = phy->channel->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void __iomem *base = drv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Skip if it's not USBHS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) spin_lock_irqsave(&drv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Power off USBHS PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) value = readl(base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) value &= ~USBHS_UGCTRL_CONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writel(value, base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) value = readw(base + USBHS_LPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) value &= ~USBHS_LPSTS_SUSPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writew(value, base + USBHS_LPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) value = readl(base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) value |= USBHS_UGCTRL_PLLRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel(value, base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) spin_unlock_irqrestore(&drv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int rz_g1c_phy_power_on(struct phy *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct rcar_gen2_phy *phy = phy_get_drvdata(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct rcar_gen2_phy_driver *drv = phy->channel->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void __iomem *base = drv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) spin_lock_irqsave(&drv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Power on USBHS PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) value = readl(base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) value &= ~USBHS_UGCTRL_PLLRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) writel(value, base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* As per the data sheet wait 340 micro sec for power stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) udelay(340);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (phy->select_value == USBHS_UGCTRL2_USB0SEL_HS_USB20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) value = readw(base + USBHS_LPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) value |= USBHS_LPSTS_SUSPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) writew(value, base + USBHS_LPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spin_unlock_irqrestore(&drv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int rz_g1c_phy_power_off(struct phy *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct rcar_gen2_phy *phy = phy_get_drvdata(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct rcar_gen2_phy_driver *drv = phy->channel->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void __iomem *base = drv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) spin_lock_irqsave(&drv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Power off USBHS PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (phy->select_value == USBHS_UGCTRL2_USB0SEL_HS_USB20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) value = readw(base + USBHS_LPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) value &= ~USBHS_LPSTS_SUSPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) writew(value, base + USBHS_LPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) value = readl(base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) value |= USBHS_UGCTRL_PLLRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(value, base + USBHS_UGCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spin_unlock_irqrestore(&drv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct phy_ops rcar_gen2_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .init = rcar_gen2_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .exit = rcar_gen2_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .power_on = rcar_gen2_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .power_off = rcar_gen2_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct phy_ops rz_g1c_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .init = rcar_gen2_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .exit = rcar_gen2_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .power_on = rz_g1c_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .power_off = rz_g1c_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const u32 pci_select_value[][PHYS_PER_CHANNEL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [0] = { USBHS_UGCTRL2_USB0SEL_PCI, USBHS_UGCTRL2_USB0SEL_HS_USB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [2] = { USBHS_UGCTRL2_USB2SEL_PCI, USBHS_UGCTRL2_USB2SEL_USB30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const u32 usb20_select_value[][PHYS_PER_CHANNEL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { USBHS_UGCTRL2_USB0SEL_USB20, USBHS_UGCTRL2_USB0SEL_HS_USB20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct rcar_gen2_phy_data rcar_gen2_usb_phy_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .gen2_phy_ops = &rcar_gen2_phy_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .select_value = pci_select_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .num_channels = ARRAY_SIZE(pci_select_value),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct rcar_gen2_phy_data rz_g1c_usb_phy_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .gen2_phy_ops = &rz_g1c_phy_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .select_value = usb20_select_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .num_channels = ARRAY_SIZE(usb20_select_value),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct of_device_id rcar_gen2_phy_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .compatible = "renesas,usb-phy-r8a77470",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .data = &rz_g1c_usb_phy_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .compatible = "renesas,usb-phy-r8a7790",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .data = &rcar_gen2_usb_phy_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .compatible = "renesas,usb-phy-r8a7791",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .data = &rcar_gen2_usb_phy_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .compatible = "renesas,usb-phy-r8a7794",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .data = &rcar_gen2_usb_phy_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .compatible = "renesas,rcar-gen2-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .data = &rcar_gen2_usb_phy_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MODULE_DEVICE_TABLE(of, rcar_gen2_phy_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static struct phy *rcar_gen2_phy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct rcar_gen2_phy_driver *drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct device_node *np = args->np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) drv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (!drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) for (i = 0; i < drv->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (np == drv->channels[i].of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (i >= drv->num_channels || args->args[0] >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return drv->channels[i].phys[args->args[0]].phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const u32 select_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [0] = USBHS_UGCTRL2_USB0SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [2] = USBHS_UGCTRL2_USB2SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int rcar_gen2_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct rcar_gen2_phy_driver *drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) const struct rcar_gen2_phy_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "This driver is required to be instantiated from device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) clk = devm_clk_get(dev, "usbhs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(dev, "Can't get USBHS clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (!drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) spin_lock_init(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) drv->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) drv->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) drv->num_channels = of_get_child_count(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) drv->channels = devm_kcalloc(dev, drv->num_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) sizeof(struct rcar_gen2_channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!drv->channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) for_each_child_of_node(dev->of_node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct rcar_gen2_channel *channel = drv->channels + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 channel_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int error, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) channel->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) channel->drv = drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) channel->selected_phy = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) error = of_property_read_u32(np, "reg", &channel_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (error || channel_num >= data->num_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(dev, "Invalid \"reg\" property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) channel->select_mask = select_mask[channel_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) for (n = 0; n < PHYS_PER_CHANNEL; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct rcar_gen2_phy *phy = &channel->phys[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) phy->channel = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) phy->number = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) phy->select_value = data->select_value[channel_num][n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) phy->phy = devm_phy_create(dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) data->gen2_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (IS_ERR(phy->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_err(dev, "Failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return PTR_ERR(phy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) phy_set_drvdata(phy->phy, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) provider = devm_of_phy_provider_register(dev, rcar_gen2_phy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (IS_ERR(provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_err(dev, "Failed to register PHY provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return PTR_ERR(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_set_drvdata(dev, drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static struct platform_driver rcar_gen2_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .name = "phy_rcar_gen2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .of_match_table = rcar_gen2_phy_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .probe = rcar_gen2_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) module_platform_driver(rcar_gen2_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_DESCRIPTION("Renesas R-Car Gen2 PHY");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MODULE_AUTHOR("Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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