^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on code from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RT_SYSC_REG_SYSCFG1 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RT_SYSC_REG_CLKCFG1 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RT_SYSC_REG_USB_PHY_CFG 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OFS_U2_PHY_AC0 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OFS_U2_PHY_AC1 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OFS_U2_PHY_AC2 0x808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OFS_U2_PHY_ACR0 0x810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OFS_U2_PHY_ACR1 0x814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OFS_U2_PHY_ACR2 0x818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OFS_U2_PHY_ACR3 0x81C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OFS_U2_PHY_ACR4 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OFS_U2_PHY_AMON0 0x824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OFS_U2_PHY_DCR0 0x860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OFS_U2_PHY_DCR1 0x864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OFS_U2_PHY_DTM0 0x868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OFS_U2_PHY_DTM1 0x86C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RT_RSTCTRL_UDEV BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RT_RSTCTRL_UHST BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USB_PHY_UTMI_8B60M BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UDEV_WAKEUP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ralink_usb_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct reset_control *rstdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct reset_control *rsthost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct regmap *sysctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writel(val, phy->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return readl(phy->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void ralink_usb_phy_init(struct ralink_usb_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u2_phy_r32(phy, OFS_U2_PHY_AC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u2_phy_r32(phy, OFS_U2_PHY_ACR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u2_phy_r32(phy, OFS_U2_PHY_DCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u2_phy_r32(phy, OFS_U2_PHY_DCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u2_phy_r32(phy, OFS_U2_PHY_DCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u2_phy_r32(phy, OFS_U2_PHY_DCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u2_phy_r32(phy, OFS_U2_PHY_DCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int ralink_usb_phy_power_on(struct phy *_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* enable the phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) phy->clk, phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* setup host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) RT_SYSCFG1_USB0_HOST_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RT_SYSCFG1_USB0_HOST_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* deassert the reset lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) reset_control_deassert(phy->rsthost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reset_control_deassert(phy->rstdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * The SDK kernel had a delay of 100ms. however on device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * testing showed that 10ms is enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (phy->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ralink_usb_phy_init(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* print some status info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) regmap_read(phy->sysctl, RT_SYSC_REG_USB_PHY_CFG, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (t & USB_PHY_UTMI_8B60M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int ralink_usb_phy_power_off(struct phy *_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* disable the phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) phy->clk, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* assert the reset lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) reset_control_assert(phy->rstdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) reset_control_assert(phy->rsthost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct phy_ops ralink_usb_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .power_on = ralink_usb_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .power_off = ralink_usb_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct of_device_id ralink_usb_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .compatible = "ralink,rt3352-usbphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .data = (void *)(uintptr_t)(RT_CLKCFG1_UPHY1_CLK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) RT_CLKCFG1_UPHY0_CLK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .compatible = "mediatek,mt7620-usbphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MT7620_CLKCFG1_UPHY0_CLK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .compatible = "mediatek,mt7628-usbphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MT7620_CLKCFG1_UPHY0_CLK_EN) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int ralink_usb_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct ralink_usb_phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) phy->clk = (uintptr_t)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) phy->base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) phy->sysctl = syscon_regmap_lookup_by_phandle(dev->of_node, "ralink,sysctl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (IS_ERR(phy->sysctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_err(dev, "failed to get sysctl registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return PTR_ERR(phy->sysctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* The MT7628 and MT7688 require extra setup of PHY registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (of_device_is_compatible(dev->of_node, "mediatek,mt7628-usbphy")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) phy->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (IS_ERR(phy->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(dev, "failed to remap register memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return PTR_ERR(phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (IS_ERR(phy->rsthost)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_err(dev, "host reset is missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return PTR_ERR(phy->rsthost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (IS_ERR(phy->rstdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_err(dev, "device reset is missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return PTR_ERR(phy->rstdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (IS_ERR(phy->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return PTR_ERR(phy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) phy_set_drvdata(phy->phy, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct platform_driver ralink_usb_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .probe = ralink_usb_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .of_match_table = ralink_usb_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .name = "ralink-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) module_platform_driver(ralink_usb_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MODULE_DESCRIPTION("Ralink USB phy driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MODULE_AUTHOR("John Crispin <john@phrozen.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags